Tag Archive: VNAND

Mar 23

News: EUVL & 3D-NAND

deadline, what deadline

February always features two conferences important to the Semiconductor Manufacturing World: The SPIE Advanced Lithography Conference and ISSCC, EUV Lithography featured prominently at the former and an update on Samsung’s 3D-NAND was presented at the latter.

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Jan 06

Samsung 3D-NAND aka VNAND

Samsung were well ahead of their competitors in the mass memory market when they announced the volume manufacturing of 3D-NAND (VNAND) chips. Some excellent descriptions of this technology notably by Andy Walker of Schilitron Inc have appeared here on the Forum and elsewhere. Initially, there was a certain amount of skepticism….

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Apr 04

ReRAM at SPIE

Following on from the last post on ReRAM related news from the SPIE Advanced Lithography Conference in February, some words on a panel session on ‘Alternative Forms of Scaling’ covering the various 3D approaches to scaling.

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Mar 10

Vertical Channel 3D NAND – An Optical Illusion?

from Andy Walker, Founder and President of Schiltron Corporation The concepts of 3D NAND and V-NAND have received so much publicity since last August that no-one should be faulted for thinking that we are on the verge of a sea-change in how high density Flash memory will be manufactured for many years to come.

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Feb 24

ISSCC 2014

Highlights from this year’s ISSCC conference included more details of the Sony/Micron 16Gb ReRAM chip and Samsung’s 3D NAND (V-NAND) chip both of which have featured in recent Forum blogs. The Sony/Micron chip is more accurately described as

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