IEDM have issued a taster/teaser (Note, link downloads the taster document) of their technical program along with session details. NVM enthusiasts will be interested in Session 10 on R(e)RAM and Session 3 which features PCRAM (its not going away!) and Flash. Session 3 has three 3D NAND Flash papers (which has a certainn symmetry, I suppose) of which includes an invited talk entitled “A Floating Gate Based 3D NAND Technology with CMOS Under Array” by K. Parat, C. Dennison*, Intel Corporation, and *Micron Technology (again a nice symmetry..) where the short ‘abstract’ released states that …. With the minimum half-pitch going below 20nm, transition to a 3D NAND cell is required to continue (the) scaling”.. As far as I can tell, Samsung do not (currently, at least) have CMOS under their V-NAND arrays (see posts here on the Forum). I’m sure it doesn’t mean anything but I couldn’t help noticing that the link to Session 3 implies it fcuses on a completely different topic (session-3-circuit-device-integration-advanced-cmos-technology-platform). Maybe a last minute change of program? BTW, Session 10’s link is exactly what you would expect given the session title!
Back to Session 10. Here, at least, there is a breakdown of symmetry as the invited talk is from just…. Micron: “Non Volatile Memory Evolution and Revolution” by P. Cappelletti. No mention of 3D Xpoint in the brief Abstract released but then one wouldn’t really expect it as I imagine the technical program was wrapped up well before the 3D Xpoint announcement. Mind you, the invitation is remarkably prescient of the program organizers! Paper 10.3 is from the HP/SK Hynix collaboration which gave me a bit of a shock. Well I say collaboration, but of the 29 authors, only 1 is from HP, the rest from SK. Few details but they have been working on a “4F2 2x-nm technology 1S1R ReRAM” (no M word in the Abstract). The S is for selector which is identified as being NbO2. Well, well…
However, what really caught my attention is the paper in the teaser from this session which is a collaboration (more equal authorwise) between the National Tsing Hua University and TSMC entitled “1Kbit FINFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process”. The teaser includes some images, here and here. While the details are brief, here’s my take on the schematics and TEM provided. The unit cell consists of two FinFETs one of which is used as a memory cell an the other as a selector. The fin is ‘engineered’ to provide an area of field enhancement at the corners where the HfO2 hi-K dielectric used in both devices can be switched. As far as I can see, both selector and memory cell have the same dielectric stack. The unit cell is quite large (265nm by 288nm). An oddity is that the larger dimension is perpendicular to the fin and shown on the schematic as smaller than the unit cell dimension along the fin. See the two images below… Maybe I’m being a bit picky, but it is odd, IMO.
Should be an interesting session….
Christie Marrian, ReRAM Forum, Director