Sep 21

Micron’s Memory Roadmap: Summer 2015

It’s that time of year again! The time when Micron’s Summer Analyst Conference (usually) provides an update on the roadmap (see Header) for their memory technologies. On the last occasion, Micron included New Memory A and New Memory B on their roadmap. Well, New Memory A was clearly 3D Xpoint and that is shown as having volume “enablement” in 2016 (a year later than last year when it was described as volume “capability”). At the end of next year, a second generation 3D Xpoint (perhaps more layers, now called “decks”) is scheduled followed by New Memory B (now called “EM Gen 1”) in the second half of 2017.

3D XPoint XSection

3D XPoint XSection

A few details of 3D Xpoint were included. The Xpoint itself is 20nm half pitch along with a cross section (XSection??). There is a cryptic reference that “It’s a great time to be a materials engineer!” superimposed on a periodic Table with several elements red lined out (including those greater than 86, H, the noble gases, Br (but not Cl) and Rb, Cs and Hg). In an accompanying video presentation, Micron CTO Scott DeBoer (sporting a very Corbyn-esque vest) made the point the crosspoint itself is not new but what is new is that Micron/Intel have managed to integrate the needed materials and structures to make crosspoint work as a high performance memory. There is also the following “Selector capable of demanding on/off currents”. IMO, this phrase is delightfully ambiguous and could mean that the selector has the capability to demand (i.e. control) the on/off currents or that the on/off currents themselves are demanding…. Deliberate? I’ll give Micron the benefit of the doubt but it is a curious wording!

Micron/Intel Floating Gate Flash Cell

Micron/Intel Floating Gate Flash Cell

Meanwhile, 2D planar NAND shrinking appears to have hit the proverbial brick wall as Micron switches to 3D NAND with 32 layers this year followed by Gen 2 and Gen 3 (more layers?) next year and 2017. Micron confirmed they are using floating gate as opposed to charge trapping supposedly used by Samsung. A schematic cartoon is included which suggests some considerable integration challenges, IMO, to isolate the floating gates with the advantage claimed that this prevents charge spreading along the charge trapping layer.

So what clues are there about EM Gen 1 (formerly known as New Memory B). Well precious little I’m afraid. ReRAM is still being developed as illustrated by a couple of images that have been used before. Spin Torque Memory get a mention along with a couple of extra details in the form of, admittedly generic, schematics and the bullet points “Early application as a high-speed cache” and “Potential long-term DRAM replacement”. No real surprises there…. However, given that details of 3D Xpoint were not even hinted at in previous Analyst Conference presentations, it seems entirely possible that EM Gen 1 will turn out to be ‘none of the above’…..

Christie Marrian, ReRAM Forum Director

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