Things have been rather quiet recently on the next generation memory/storage front, when suddenly, out of the blue, there is a dramatic announcement from the ~10 yr old Micron/Intel NVM collaboration that recently announced a shift to from planar to 3D NAND. At a rather spartan 45min press conference/webcast, Rob Crooke, Senior VP of Intel’s NVM Group and Micron CEO, Mark Durcan announced a ‘new’ memory/storage technology based on a cross point array of cells comprising a ‘bulk switching’ memory cell in series with a selector device. Impressive numbers were quoted for performance benefits compared to NAND but the much repeated theme was that this was not so much a DRAM and/or NAND replacement but a new technology that filled the space between the two technologies, i.e. it is non-volatile, fast (-er than NAND) and low (-er than DRAM) power. Cost wise it is expected to fall between NAND and DRAM as well which is perhaps not that surprising….While a 300mm wafer of 3D XPoint 128Gb chips was unveiled towards the end of the first part of the webcast, few technology details were revealed beyond it being a ‘bulk’ mechanism (I assume, this meant not filamentary). The chips comprise two stacked arrays of 64Gb each and they were described as scalable both laterally (smaller dimensions) and vertically (more layers). While no dimensions were given the back of my envelope suggests that the crosspoint pitch should be towards the lower end of the 40-50nm range.
The chips are in production in Lehi, Utah and products (brought to market by Intel and Micron separately) are projected for next year. The process development and integration was ‘hard’ (an understatement, IMO) and the results of combined efforts of the Intel and Micro development teams with more than 100 engineers being involved in total. Some rather cryptic remarks were made about the materials involved which suggested this is a new material set but not completely off the wall.
In view of the lack of technical details, the internet did what it does so well in that it allowed folks to discuss (and speculate) what the physics and materials might be. Some of the good folks over at EETimes unearthed this presentation (note: link downloads the file) from DerChang Kau from Intel at the 7th International Symposium on Advanced Gate Stack Technology in 2010 where options for candidates for crosspoint PCM (phase change memory) technology is described. More recently the Dr Kau has co-authored a patent application entitled “Self-aligned cross-point phase change memory-switch array” US20150001458A1 but as an employee of Micron. (I believe this suggests that DerChang was part of Numonyx which was spun out of Intel and eventually bought by Micron.) This would imply that the new technology could be based on a phase change memory cell and a threshold selector device (often described as PCMS). Personally, I find this unlikely as phase change being a thermally driven mechanism has crosstalk and power issues. But I should add I can find no paper trail pointing to another material set and switching mechanism.
Another interesting question is why make the announcement now? Sampling is supposedly ‘by the end of the year’ so is a way off. As I mentioned, the setting for the webcast looked somewhat spartan and suggested to me it might have been hurriedly put together. Also in contrast the recent (March, when samples were already available) 3D NAND webcast made by the same collaboration where 4 VPs participated, the CEO of Micron took part in the announcement of 3D XPoint. More speculation, but Micron is currently the subject of a hostile take-over and has a languishing share price. Certainly now would be a good time for a fillip and Christmas may be too late. Indeed, MU is up nearly ~8%% over the past couple of days.
Christie Marrian, ReRAM Forum Director
p.s. More evidence that 3D Xpoint is PCM or PCMS (PCM plus Switch or Selector) based comes from Jason Mick at the Daily Tech. He is certainly convinced. I was struck by this recent Patent Application from Micron: US20150074326 A1: “Accessing Memory Cells in Parallel in a Cross Point Array”. The described embodiments of the cell/selector are phase change memory cells with OTS threshold switches/selectors. The word ‘Chalcogenide’ appears 23 times in the application compared to zero times for ‘Oxide’!
Also the Micron/Intel presentation does not make any reference to this being an inherently low power technology beyond the elimination of the need for DRAM refresh. I wonder how they have solved the thermal budget and crosstalk issues….