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Apr 21

ReRAM that you can buy (and tear apart)

I’ve mentioned TechInsights in previous articles on the Forum. They provide a literally ‘unique’ service in providing a view of the insides of chips revealing much about the dimensions, materials and structure of the various components. Memory chips are no exception and their latest reports are of particular interest to the ReRAM community as they feature an Adesto 128 kb CBRAM chip and the Panasonic MCU with 64kB of embedded ReRAM. Another important aspect of these reports is that they show that these chips are not just the hardware equivalent of ‘vapourware’ but that they actually exist. In this day of frequent announcements of groundbreaking developments which somehow never actually make it to the marketplace, TechInsights’ reports are an important validation that a particular technology has made it into production. So what can we learn from these reports.

Adesto’s CBRAM, integrated in a 130nm logic process

Adesto’s 1st CBRAM product integrated in a 130nm logic process

There’s a summary from Kevin Gibb, Product Line Manager, Process, TechInsights on EETimes which is definitely worth a read. The Adesto chip is described as RM24EP128KS which does not bring up any ‘hits’ on the Adesto web site although RM24EP128A does and is a 128kb part from Adesto’s medical offerings. The TechInsights images are similar to these to the left from Adesto except that dimensions are included and materials identified.

A couple of things stood out for me (and indeed Kevin). The Adesto chip has a 1T1R configuration and a seemingly low array efficiency which my eyeball estimate reckons is barely 50%. The chip is ~1.5mm square(ish) fabricated with 130nm technology by Altis Semiconductor. I don’t have precise details of the chip layout but the back of my envelope tells me that you can build a lot more than 128kb of memory at such design rules in even 50% of the estimated chip area. So maybe there is actually more memory in the chip than that which is actually used or (as a comment to the EETimes article suggests) the extra is for added redundancy. In any case, it suggests that far higher capacity chips should be available from Adesto fairly soon.

The other thing that struck me was the materials identified*: silver for the top electrode and germanium sulfide for the solid electrolyte in which the conductive bridge is formed. While it is notable that Altis have solved the problems associated with the introduction and processing of these materials in their Fab, as Kevin Gibb points out, it does rather limit the other technologies and Fabs in which these chips can be manufactured. Again, I’m sure Adesto are working on this and I wouldn’t be at all surprised if a less exotic material set appears in a subsequent teardown of future Adesto chips.

The Panasonic MCU is fabricated with an 180nm CMOS process although the ReRAM cells are fabricated at close to 500nm half pitch in between M3 and M4 according to TechInsights. The cell is tantalum oxide based which, if the cell is as has been described by Panasonic is a bilayer of two different stoichiometry oxides. There is a tantalum ‘based’ bottom electrode (TaN?) and iridium is used for the top electrode which as far as I can see is the most ‘exotic’ material used. As an aside the M3 & M4 metal layers looked etched rather than damascene so are presumably not copper but aluminium. The TechInsights cell image is similar to that below from Panasonic except that Panasonic show the metal as ~1um half pitch!

Panasonic ReRAM

Panasonic 1T1R-ReRAM Memory Cell


The area of the ReRAM memory is not identified in the full chip image but based on some of Panasonic’s cartoons it could be the large dark area in the bottom right which looks to be around 1mm2 in size. Again this is larger than would be expected on the basis of the design rules and the stated 64kB capacity. However, the data sheet states that the ReRAM memory is split between program and data memory with the latter having a 100x the endurance of the former. So perhaps this is achieved through redundancy, unless of course, I am doing my back of the envelope calculations on the wrong area of the chip (which is entirely possible).

Christie Marrian, ReRAM Forum Director

*Please see comment below for more details on the materials used in Adesto’s CBRAM

1 comment

  1. Sam

    Hi Christie,

    Sam writing from Adesto. Nice to “meet” you, and thanks for taking a look at our tech.

    Unfortunately, Kevin’s article on EE Times contains a bunch of out-of-date information, especially on the materials we use in CBRAM. Those are years old!

    We’re working with EE Times to have this corrected. In the meantime, below is the information we provided about what was wrong with the article.

    Clearly, this isn’t your fault at all, but it’s pretty important to us to have correct information out there. If you wouldn’t mind getting back to me, just to say you got this and would update, that would be much appreciated!!

    Thanks so much.
    Best,
    Sam

    1) Adesto’s CBRAM manufacturing process does not use silver/germanium sulfide/tungsten materials. These were first generation process materials (never used in production) which had serious limitations related to manufacturing and application. ( see http://electronics360.globalspec.com/article/4332/ceo-interview-adesto-s-derhacobian-looks-to-move-cbram-to-asia).

    2) The image shown in your article representing a CBRAM cell is a 1st generation cell. No production device (including the RM24EP series you mention) uses this combination of materials.

    3) Adesto has been manufacturing discrete memory devices using CBRAM with current improved resistive stack materials since 2012 (cited, as you correctly refer to, in our paper presented at IEDM 2013. This paper, submitted mid-2013, outlined some of the limitations of the GeS2cells.) These changes were absolutely essential to ramping the technology into high volume manufacturing.

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