February always features two conferences important to the Semiconductor Manufacturing World: The SPIE Advanced Lithography Conference and ISSCC, the international Solid-State Circuits Conference. EUV Lithography featured prominently at the former and an update on Samsung’s 3D-NAND was presented at the latter.
EUVL’s progression to manufacturing has been (and continues to be) a sobering saga of unfulfilled promises and missed deadlines. (Here’s a ‘nice’ review of the past decade(s) entitled “100W by the End of the Year“ from Lithoguru, Chris Mack ) However, development still continues although there is now effectively only one supplier of EUVL scanners, namely ASML. Given the co$t, this was probably inevitable but it does mean that that competitive edge which drives most (if not all) development in the semiconductor field is missing.
The focus (no pun intended) over the past few years has been on increasing the EUV source power to a level where volume manufacturing becomes at least contemplatable (sic). The point being that it does not matter how good the rest of the Lithography system is, if you can’t get enough photons to the wafer. 100W has long been the goal and this year there has finally been some good news in terms of approaching (if not actually reaching) that goal. Several scanners have been running with 40W source power and at least one (at TSMC) with ~80W. TSMC reported on this at the SPIE Conference and described a 24 hour continuous run when over 1000 wafers were ‘exposed’. As an aside, it is never a good sign when a metric of performance is changed. Normally scanner performance is quoted in wafers per hour but, for some reason, EUVL practitioners have decided on wafers per day…..
It is not clear (to me at least) that any resists were exposed during the TSMC run (or similar runs at 40W performed by IBM) or that overlay was performed and measured. This has been described as equivalent to showing that a photography flash gun can produce a given number of flashes without actually telling you anything about the quality of the photographs! .
But still it is a start and an indication that the EUVL is within a factor of ~3 of that required for volume manufacturing at today’s leading edge nodes. Now, I suspect the ‘fun’ will really start as the lithographic quality and performance of the scanners is studied at more realistic throughputs.
Over at ISSCC, Samsung reported on ‘A 128Gb 3b/cell V-NAND Flash Memory with 1Gb/s I/O Rate’. Andy Walker has written a nice review including an image which compares the 128Gb 3b/cell version reported at ISSCC 2015 with the 2b/cell 128Gb chip reported at ISSCC 2014. Samsung appear to have taken one of the two planes from the 2b/cell chip and doubled its capacity by going from 24 to 32 layers and 2b/cell to 3b/cell. The array circuitry is a little larger than half of that on the 2b/cell chip.
Reaching for an envelope with unscrawled upon back, I estimate the minimum pitch of the metal layers in the word (row) and bit (column) line directions to be~42nm which is close to Techinsights measurement of 40nm from their teardown of the 86Gb 3b/cell chip shown in the middle of Andy’s image. This looks like a~15% lithographic shrink of the metallization to accommodate the extra layers resulting in a slight fattening of the page buffer in the periphery.
Christie Marrian, ReRAM Forum Director