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Jan 22

Patent Alert: US8861258

US Patent 8861258A recent patent granted to SanDisk describes a “Set/reset algorithm which detects and repairs weak cells in resistive-switching memory device”. One of the inventors was kind enough to alert me to this and describes the importance as follows: “One of challenges about ReRAM is to set stable On/Off states at very low current. It is common to observe ‘Relaxation’ and poor data retention, particularly at low current set/reset. The method described in this IP (US 8,861,258) uses disturb pulse to find and fix weak bits effectively in terms of time and power.”

The key claims of the patent refer to the method and memory device where a stability test phase is applied to the memory cell after a set or reset programming operation. The stability test phase comprises applying one or more disturb voltages to the memory cell and performing a stability verify test for the memory cell. Based on the number of times the memory cell passes the stability verify test, a decision is made on whether further programming of the memory cell is warranted.

An important part of the IP is the basis of the algorithm behind the stability test phase. The patent describes a variety of ways the disturb pulse (e.g. a shorter programming pulse, same or different polarity, ..) is applied and how the results are analysed to decide on whether a subsequent programming phase is needed. This is illustrated by one of the figures from the patent below. The programming voltage is ramped until the subsequent read indicates the cell passes the program condition (1st programming phase). In the subsequent stability test phase (designated by 910 in the figure) a shorter programming pulse is used as a disturb pulse. One example of the stability test phase is to repeat the disturb and subsequent read pulses (e.g. 911 and 913) a number of times (just two are shown in the figure) and count the number of times the cell that the read current is within acceptable bounds. If the number of passes is greater than a preset threshold, stability is verified and a second programming phase (920) is not performed.
US 8861258, Figure 9

There is obviously a lot of flexibility in the way the disturb pulses can be applied and the stability test phase is performed and the patent describes many such examples. The patent also describes some of the trade-offs between the complexity (i.e. time required) of the stability test phase and the resulting improvement of memory cell stability.

The patent is actually quite easy to follow (which is not always the case) so my congratulations to the authors and preparer of the documents! While this patent was filed in 2013, it does suggest that SanDisk is committing resources to ReRAM. A quick search of the US patent office web site shows applications being filed in 2014, both by SanDisk authors and in collaboration with Toshiba and Intermolecular (see Blogs passim).

Thanks Zhida!
Christie Marrian, ReRAM Forum Director

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