Jan 06

Samsung 3D-NAND aka VNAND

Samsung TCAT, VLSI 2009

Samsung TCAT, VLSI 2009

Samsung were well ahead of their competitors in the mass memory market when they announced the volume manufacturing of VNAND chips. Some excellent descriptions of this technology notably by Andy Walker of Schilitron Inc have appeared here on the Forum and elsewhere. Initially, there was a certain amount of skepticism as it was essentially impossible to find any actual products using VNAND let alone the chips themselves. However, this has changed and products (enterprise SSD’s) and chips have been found and tested. The performance of the VNAND containing 850 SSD has been compared to its planar counterpart, the 840 by the Memory Guy, Jim Handy. As expected, the 850 outperforms the 840 in most of the tests but and Jim points out some interesting differences in power consumption. Incidentally, both products use the same ‘MEX’ controller so some further performance gains might be expected with a controller dedicated to VNAND in the future.

TechInsights have got their hands (grinders, polishers, SEMs and TEMs) on the second generation VNAND chip which has 32 (rather than 24) layers of charge trap memory cells. According to TechInsights the chip has “3 levels of metallization (1-W, 1-Cu, 1-Al), tungsten vias and contacts, and polycide peripheral gates. The part features a 40 nm minimum pitch metal 2 bitline in the array”. Andy was quick to grab this new data as it allowed him to refine his cell size analysis. His article also has some remarkable SEM and TEM images from TechInsights. The bottom line is that the VNAND chip has a ~20F2 cell size with F = 40nm (the relevant half pitch of the memory array). Andy compares this to Samsung’s planar NAND which has a ~4F2 cell size with F = 16nm and estimates the VNAND cell size is some 24 times larger. Taking into account the number of layers (32) and the number of bits/cell (2 vs 3, I believe) the difference in area per bit works out to be 8/9 in favour of the planar 3bit/cell NAND. The array efficiency appears also to be slightly better in the planar chip. However, the VNAND has better performance driven by the architecture and also being MLC as opposed to TLC.

As a quick aside, I’d always assumed that the periphery circuitry could (in theory) be built underneath the memory arrays (as in ReRAM). Actually this is not possible in Samsung’s architecture as the substrate is use for the NAND string select transistors as seen in one of the TEM/SEMs. (From TechInsights “The vertical NAND cell string has 32 word line stacked layers, 4 dummy cells, and 2 select transistors stacked in a vertical direction.” i.e. 38 in total)

So, assuming the chip manufacturing, packaging and test costs are comparable (huge assumption), VNAND needs to have more layers to get to a comparable cost per bit as planar NAND which would open up the vastly larger cost driven stand-alone memory/storage market to the technology. This as Andy has pointed out, is not as simple as just ‘adding’ a few more layers as there will be also sorts of complications due to the reduction in currents resulting in the longer polysilicon channels of the vertical NAND strings. However, I have no doubt that Samsung will soon release a 3rd generation VNAND chip with 48 layers.

Chip manufacturing costs are driven by the number and complexity of the processing steps and the yield of the manufacturing process. (For a memory volume manufacturing process, it turns out that these tend to be greater than other items such as mask costs, capital depreciation and fab building costs.) I, of course, have no knowledge of the relative yields of planar and 3D NAND beyond speculating that the newer technology has a lower yield which will improve with the passage of time (and the number of parts manufactured).

Samsung 86Gb Die

Optical micrograph of Samsung 86Gb chip (TechInsights)

One of the most challenging layers in NAND is the first metal layer. Typically this has arrays of lines at minimum pitch in the word and bit line directions. To make matters worse, there are inevitably some far larger features as well. This often requires multiple masks and the added complexity brought by double patterning.  Does 3D NAND have any advantages in terms of a simpler metal layer? At first look, probably not. According to TechInsights, the tightest metal pitch is 40nm which will require double patterning. Further, looking at Andy’s cartoons, this critical pitch will be required in both directions on the chip. There needs to be contact with adjacent rows of the vertical bitlines and, in the wordline direction, all 38 layers need to be contacted within the larger dimension of the unit cell. It looks as if there are wordline drivers on both sides of each of the two planes (see above) so possibly only 19 need to go out each way. This corresponds to a pitch of close to 40nm….. 16nm planar NAND, on the other hand, requires a 32nm pitch metal in both bit line and wordline directions along with matching features on at least two other layers. Both technologies will have some (very) critical contacts.

Bottom line? Speculation on my part but I suspect that VNAND is more expensive to produce due to a larger number of processing steps and, at present, the lower yield than planar, even though the tightest pitch is greater (40nm vs 32nm)

Happy New Year!

Christie Marrian, ReRAM Forum moderator


  1. Fred Chen

    The “40 nm minimum pitch metal 2 bitline” does not mesh with the pitch F=40 nm deduced from Figure 6 scalebar. In fact the ONO thickness does not mesh with the scalebar either.

    I think you have to compare with the 16 nm MLC planar NAND overall chip size at same density.

    1. admin

      Hi Fred
      Thanks for the comment! The 40nm pitch is a direct quote from TechInsights. I agree that based on the images available, 40nm pitch is not needed in the bitline direction as 80nm pitch would appear to suffice. Maybe there is something else involved. Intetestingly my back of the envelope calculation suggests that 40nm pitch might (I stress might) be needed in the wordline direction.
      Figure 6 in Andy’s article is a remarkable TEM, the sample prep must have been incredibly difficult. I see it as showing the gate (dark areas) surrounding the holes which have three concentric rings followed by a thicker 4th ring which looks like the poly channel. Samsung TCAT is supposedly a TANOS cell so the outermost ring would be alumina hi K followed by the nitride trap layer and the oxide tunnel layer. The combined thickness of all 3 layers looks as if they add up to ~22nm.
      Jim Handy has a nice description of the ‘gate replacement’ TCAT process.
      Best, Christie

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