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Jul 01

Millionth, MegaBytes and Machine

millionNews from HP, Crossbar and Adesto Technologies who have just announced the shipment of their millionth CBRAM product. Quite a milestone for a next generation technology product.

I suspect that in Adesto’s case this interest is driven not so much by concerns about scaling of Flash memory (Adesto’s CBRAM is all low density) but rather by the lower operating power. This has become a huge deal for the development of the next cycle of interconnected objects, a.k.a. the Internet of Things (IoT). Minimizing the load on the battery (or eliminating the need for chan(r)ging) is now a major issue for wearables and medical devices, for example. Narbeh Derhacobian, Adesto’s CEO puts the issue into context: “The adoption of CBRAM technology demonstrates the need for a new class of application-specific memory to enable the next generation of connected devices. Devices based on CBRAM can operate with significant reduction in power consumption, allowing longer battery life. This powerful capability will enable previously unimagined products such as the autonomous connected devices that are critical to the Internet of Things.”

Crossbar has also been in the news with the appointment of Ron Richter as vice president of sales and more details of their memory architecture. They have ‘demonstrated pre-production 1MB arrays using its patented “1TnR” (1 Transistor driving n Resistive memory cells) selectivity for read/write operations’. The one transistor drives an array of some 2000 memory cells avoiding the problems of “sneak path current” in crossbar arrays to provide very low power and dense memory. In a separate report that I could not find on Crossbar’s website, Tanmay Kumar, vice president of device engineering is quoted as saying that 8MB memory will be available for evaluation from 2016 with terabyte chips shipping a few years later.

Low power is also at the center of HP’s latest pronouncement involving their ReRAM (memristor) technology. The company has been quiet recently as the latest date for the availability of their memristor came and went. However all that changed dramatically on June 11th at the HP Discover event in Las Vegas where The Machine was unveiled by CEO Meg Whitman and CTO Martin Fink. The announcement has received a fair amount of press but I had a hard time tracking it down on an HP web site. I eventually found this video on a page titled with the next HP Discover event (in Barcelona in December). The presentation is not the easiest to follow (and indeed the audience seemed to having a hard time too) and some of the numbers didn’t seem to add up. Below is a clip from the video showing some key characteristics of The Machine. However the back of my envelope indicates that the number of processors (8 racks*256 SoC/rack *24 cores/SoC) would be 49k, not the 122k given and the total memory (8*256*256 GB/SoC) would be ~0.5 PB rather than 1.3 PB. My envelope couldn’t make sense of the claimed power numbers which suggest about one W per 2 GHz core. The memory is based on their memristor technology but the cores are ‘conventional’. The SoCs and/or racks are connected photonically summarised in one slide as
Electrons – Compute, Photons – Communicate, Ions – Store!

hpmachineperformance

HP pointed out that a lot of the time and energy of computation is used by the OS (operating system) moving data between the various levels of the memory hierarchy (SRAM, DRAM, Flash/HDD) of existing computer architectures The Machine has one level of Universal Memory which the OS will be developed to use optimally. The memory would presumably be the ~10 GB per core in each SoC along with a photonically connected memory ‘pool’ with a byte addressable speed of <250 ns. While impressive this would seem to be much slower than the on-SoC memory so at least two memory levels would appear be needed.

The final slide gives a timeline (‘Future History’) for the project. This includes
2014: Memristor media controller protocols and standards established, Machine OS development begins,
2015: Memristors begin sampling, Open source Machine OS SDK released,
2016: Memristor DIMMs launched,
2017: Machine OS public beta,
2018: Machine OS released,
2019: Core devices ship, Machine available as product
2020: Distributed mesh compute goes mainstream.

Welcome (to) The Machine!

Christie Marrian, ReRAM Forum Moderator

4 comments

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  1. Fred Chen

    What is the density of the Adesto CBRAM now?

  2. admin

    Adesto’s CBRAM is currently available in 32kb to 1Mb density.

    1. Fred Chen

      Thanks, I just checked the same source, so maybe that was too easy :)

      If the IoT is all about lowering power, is there a reference? I suspect “as much as possible” is the sought answer since we’re adding functionality, but some things like read current should be handled carefully.

      1. admin

        This is much more difficult! For some devices powered by energy scavenging every pJ is critical so even read current is an issue. For others there is an energy budget which has to be divided up between the various tasks of the device over the device lifetime. Reducing a component’s energy requirement “as much as possible” could perhaps be modified to “to much less than competing technologies”. I am unaware of any standards and power consumption for some IoT devices is not an issue if, for example, they are already powered. A CR2032 holds a kJ or two so if the device has a 5 year lifetime/battery change requirement, one is back to “as much as possible”!

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