Following on from the last post on ReRAM related news from the SPIE Advanced Lithography Conference in February, some words on a panel session on ‘Alternative Forms of Scaling’ covering the various 3D approaches to scaling. The panel comprised of luminaries from Micron, Xilinx, SanDisk and ReRAM Forum sponsor, Adesto Technologies. The panel was put together by Professor Philip Wong of Stanford University and Chris Bencher from the CTO’s office at Applied Materials. Chris is an interesting guy and introduced our team at Spansion to the seeming magic of self aligned double patterning (SADP) some years ago. Some of this work was published in Semiconductor International and gave a nice primer on SADP but sadly the journal is no longer with us.
Johann Alsmeier of SanDisk pointed out the advantages of 3D NAND flash in the context of scaling limits of high-voltage program/erase, decreasing storage charge, and cost which is now being driven by etch and deposition rather than lithography. 3D should bring improved performance in terms of increased endurance, higher write speeds and reduced power echoing similar remarks from Samsung.
Liam Madden from Xilinx discussed heterogeneous stacking for FPGA products. Here the issue is combing of disparate technologies (logic, memory and analog) with disparate feature sizes into a single package which is being addressed through silicon interposers.
3D stacking is also seen as a solution for DRAM as described by Kunal Parekh of Micron Technology who are pursuing the hybrid cube memory (HCM). DRAM scaling will be limited the capacitor module rather than lithography. Stacking DRAM addresses bandwidth concerns by enabling higher densities and efficient power use while increasing capacity.
Michael Van Buskirk of Adesto Technologies presented the case for 3D ReRAM. Mike introduced the different ReRAM switching schemes and demonstrated a path from the DRAM 6F^2 cell to a 4F^2 crosspoint cell. Mike highlighted the path to 3D ReRAM by comparing stacked cross-point and vertical ReRAM schemes.
He pointed out that vertical ReRAM provides a scaling advantage over vertical (3D) NAND architectures for a couple of reasons. In vertical NAND the (vertical) bit lines must be silicon as it forms the channel of the storage devices. In vertical ReRAM, the (vertical) bit lines are one of the cell electrodes and usually metal. He contrasted the via size required for vertical ReRAM (~40nm for electrode and ReRAM stack) to the larger via required for vertical NAND to accommodate the Si channel and charge trapping layers (~65nm). This leads to a reduced bit line pitch. For ReRAM the (horizontal) word lines and interlayer dielectric can be made thinner. Using the example of a DRAM capacitor (which is the highest aspect ratio via structure in volume production) with an aspect ratio of >20:1, Mike pointed out that the vertical NAND architecture could have 20+ layers, close to that in Samsung’s recently announced VNAND chip.
A lively Q&A session completed the evening and identified key issues such as thermal management, stress control, defects, 3D metrology, along with the integration of new materials.
Christie Marrian, ReRAM Forum moderator