Mar 20

SPIE Advanced Lithography Conference

The SPIE Litho conference every February is one of the things I really miss being located this side of the Pond. I used to attend regularly starting when it was held at the San Jose Fairmont. I was involved in running one of the sub conferences and participated in various sessions and panels. The great thing about the conference is that everyone is there and more often than not there is more animated activity in the hallways than in the actual sessions. These days, of course, it’s called Networking!

This year, the conference saw a continued increase in attendance and gave everyone the chance to find out how EUV lithography is doing. Not great seemed to be the general consensuses although, manufacturing capable tools are now operating in the field (or rather Fab). Not entirely unsurprisingly these first results from tools in operation have thrown up all sorts of issues. The TSMC tool for example suffered “a disaster with misalignment of the 200kW laser that damaged some other components” (although was reported to be up again at the time of the conference). Defects on masks have improved but only enough to show up another problem, that of defects (particles) added during handling and use of the mask in the stepper. This is a well known problem and is mitigated with UV lithography steppers by a transmissive pellicle which covers the mask with a slight gap between pellicle and mask. This prevents the particle defect from landing on the mask and being in focus. At EUV wavelengths most materials are so absorbing that a pellicle has proved elusive. A thin polysilicon pellicle is being developed by ASML but it is currently just over a ¼ of the full mask size and is projected to have thermal issues at manufacturing illumination levels.

Delays in EUV lithography have been substantial and consistent from year to year. Usually it is the proponents of competing next generation lithography technology that have made this point. However, this year, EUV proponents themselves have been really emphasising these continued delays. Source power has long been an issue (and still is) with each year the source power roadmap in the shape of a hockey stick shifted out more or less exactly one year. Jack Chen from TSMC superimposed some of these ‘roadmaps’ onto one slide which makes pretty sobering viewing. However it turns out that Intel (another long time EUV proponent) had beaten them to the punch back in November last year with much the same slide entitled “Source power roadmap has lost credibility”! The full slide is very detailed so a section is shown here. The source power for volume manufacturing is ~250W @intermediate focus which is just off the top of the figure. The crosses marked levels measured in tools in a Fab (as opposed to a Lab, star symbol) to date…..

Unfortunately, this is not good news for ReRAM, at least as proposed by manufacturers such as SanDisk who have repeatedly said that EUV is required for their approach. I do not know for certain why this case but I can (and will) speculate. The SanDisk/Toshiba approach described at ISSCC 2013, is based on stacked crosspoint arrays built on top of a CMOS control circuitry. The wires in the crosspoint arrays are nice parallel arrays which are one of the easier geometries to define by multiple patterning such as spatial frequency doubling/quadrupling. This is done routinely in today’s NAND chips. However, contact vias are much more difficult this way and require multiple exposures which is even more costly that spatial frequency doubling. There are also problems arising from overlay errors between the multiple exposures. Dense arrays of contacts (which may be required within the contact array) are particularly problematic. Contacts are also required to connect the ends of the crosspoint arrays down to the underlying CMOS circuitry. These can, in principle, be spaced out more than a dense array but they are absolutely essential for the chip architecture. And the more they are spaced out, the smaller the chip array efficiency and hence the higher the cost per memory unit. EUV has the promise of being able to print such contact arrays with a single exposure and indeed, ASML (the main EUV lithography tool developer) showed 17nm HP contacts and 13nm HP lines at the November EUV source workshop.

More from SPIE in a week or two (I hope)

Christie Marrian, ReRAM Forum Moderator


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  1. Fred Chen

    If the half pitch of the ReRAM array is 40 nm or more, EUV is not necessary. 3D stacking can improve the density without advanced lithography. SanDisk/Toshiba already do this. So I don’t really see the tie to EUV. EUV is already known to have trouble with shot noise for small contacts.

    1. admin

      Hi Fred
      I was referring to the SanDisk/Toshiba 32Gb ReRAM chip presented at ISSCC in 2013 which is described as fabricated with 24 nm technology. Shot noise is indeed a problem in EUV but, in theory, you can use a resist which is sufficiently insensitive that shot noise is not an issue. However, this merely adds to the source power requirement!

      1. Fred Chen

        You are right about using less sensitive resist and more power.

        I checked the 32Gb ReRAM details at this link: http://techon.nikkeibp.co.jp/english/NEWS_EN/20130221/267306/

        It seems that the cells are etched as intersecting crossed lines. And there are published tricks for single-exposure pitch-halving with spacers. In that case, I don’t see lithography being a limiter at all for the cell definition.

    2. admin

      My apologies. Today (March 20th) is International Happiness Day and the First Day of Spring being celebrated by a great Google Doodle. I can’t think of a less appropriate day to discuss EUV lithography…..

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