Mar 10

Vertical Channel 3D NAND – An Optical Illusion?

from Andy Walker, Founder and President of Schiltron Corporation

The concepts of 3D NAND and V-NAND have received so much publicity since last August that no-one should be faulted for thinking that we are on the verge of a sea-change in how high density Flash memory will be manufactured for many years to come.
In addition, it certainly appears that other forms of 3D-stackable nonvolatile memories, including ReRAM approaches, will have to wait for several technology generations (5 according to Samsung at the recent International Solid-State Circuits Conference (ISSCC)) before they enter into contention.
Anyone who has followed my 3DIncites blogs will know that I do not share the enthusiasm for these “litho-light” 3D NAND approaches. To counter the criticism that all these comments are simply self-serving plugs for my company’s rival 3D Flash technology, I have stuck to peer-reviewed discussions and experimental data.
Here, I would like to explain myself and show that there is plenty of opportunity for any monolithic (i.e. non-chip-stacking) 3D stand-alone nonvolatile memory. To do so, I will deal with two major aspects that form the foundation of any approach, namely cost and performance, and apply these to Samsung’s V-NAND.

When these vertical channel 3D NAND approaches first came out (BiCS from Toshiba in 2007 and TCAT from Samsung in 2009), cost was emphasized as being the primary driver behind them.
The first real rumblings about their cost challenges came in 2012. First was a study from the University of Tokyo (Yanagihara et al.) where the vertical channel was shown with a taper angle that was included in the effective cell size. Then an SK Hynix paper (Choi and Park) stated that “the unit cell size also increases as the stack height”. Finally, Intel/Micron (Goda and Parat) came out with “a near vertical pillar profile is a key to achieving effective cell area scaling over 2D NAND”.
What seemed to be missing was a total chip cost model based on these effects. For this, I built on the foundations laid by others and finally came out with the IEEE Transactions on Semiconductor Manufacturing paper last November. It’s Open-Access so free to download.
Figure 1 shows a generic vertical channel 3D NAND with the structural parameters used.

Figure 1 – A generic vertical channel 3D NAND with structural parameters used in the IEEE cost model paper.

The most important conclusion from this study is reproduced here: “A general principle can be gleaned from this study. It is that any high density 3D Flash approach that exchanges lithography-intensive processing per device layer for a stack deposition followed by deep hole and/or trench etching must result in taper angles of zero or close to zero degrees. Otherwise, its total cost can be undercut by any 3D process that uses lithography per device layer to minimize cell areas on all layers.”
What this paper did was to show what kind of cost straightjacket these approaches are trussed up in. What was missing was a real cell size.
This finally came, not explicitly but after some calculation, on February 12th this year at the ISSCC. And it was actually worse (better for the rest of us) than I thought. Samsung’s V-NAND cell size at the top of their stack is about 30 times that of the most advanced 2D NAND (Micron’s at the 16 nm node). For the full comparison, see the 3DIncites article. Figure 2 is taken from that article to emphasize this point. In addition, Samsung’s presentation stated that they would stay at the 40 nm node all the way to 1 Tbit which means there is little leeway to shrink the cell laterally. It appears the only way to increase single chip capacities then is to stack more layers and so increase the length of the NAND strings. This then takes us nicely to performance.

Figure 2 – A generic vertical channel 3D NAND with approximate cell dimensions in red at the top of the stack derived from Samsung’s 2014 ISSCC presentation. The blue rectangle is the size of a 2D NAND cell at 40 nm node. The yellow rectangle is a 16 nm node 2D NAND cell.

Since lengthening of the NAND string looks like the main if not only way to increase vertical channel 3D NAND capacities, one performance parameter sticks out like a sore thumb, namely the string current. This is the amount of current to expect out of a string when reading the state of a cell. The important value is the worst case string current which is the value when an erased state cell is being read while all others in the string are in the programmed (and therefore high impedance) state.
Since this parameter is hardly ever mentioned, we at Schiltron have measured it by configuring our memory strings as if they were NAND strings. The key is that the channel has a disordered structure which lowers the mobilities of the charge carriers.
Figure 3 shows the string current as a function of over-drive voltage applied to the gates of the cells connecting up the one being read to the ends of the string. The read pass overdrive voltage is the difference between the voltage applied to these passing gates’ and their threshold voltage. If they are all in the erased state, then we have the best case string current. If they are all in the programmed state, then we have the worst case. Boosting this over-drive voltage would increase the worst case string current but at the expense of disturbs.
Samsung will need 192 cells in a string to get to 1 Tbit with their V-NAND architecture. This will result in a worst case string current close to a nanoAmp. This is orders of magnitude away from what is currently sensed.
If you want to dig deeper into this vanishing string current problem, see the two 3DIncites articles that deal with it. There is also a Schiltron whitepaper that gives even more depth.

Figure 3 – Experimental string currents from NAND strings with polycrystalline channels.

From both a cost and performance point of view, there is still plenty of opportunity for any 3D stackable nonvolatile memory technology without having to wait too long. This is why we at Schiltron are excited since we have solved the performance problems mentioned above and at a smaller cell size that leads to a lower cost.

And of course these are precisely the same reasons why those involved with 3D ReRAM can also take heart!

Andy Walker, Founder and President of Schiltron Corporation Schiltron Corporation, Mountain View, California, www.schiltron.com. Andy can be contacted at: [email protected]


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  1. scranton

    Re the taper angle consideration, isn’t the quantitative analysis significantly changed by one litho defined layer in the middle and two stacked deep trenches instead of one deeper deep trench ? The optimum might even be a few more litho steps.

    1. andyjan123

      Thanks “scranton” for your comment. Yes, that would be a possible way to keep within the straitjacket boundary conditions of taper angle. It turns out though that even at the 24 layers in this v-nand, the cell at the top of the stack is very large. It seems that other things are defining this size. This is probably not surprising given all the parameters that form the pitches of the cell. I wrote about this elsewhere http://bit.ly/1hY4j77
      In addition, the vanishing string current conundrum remains.

      Regards – Andy

      1. Fred Chen

        Would the string current issue be resolved with a horizontal instead of vertical channel?

    2. Fred Chen

      Yes, I agree with scranton that there is a difference. Toshiba when they first published the BICS also divided their 16 layers into two processing iterations each involving 8 layers. It makes sense since I imagine with more layers it will be harder to see the substrate for patterning alignment. But this said, I would be even more curious now how Samsung does the 24 layers of their V-NAND. If it is one shot (the photos are not clear enough) that would be quite impressive indeed.

  2. andyjan123

    Thanks Fred for your comments. Going horizontal means that the string length becomes of secondary and not primary importance in determining chip size. Therefore, shorter strings could be used. However, certain challenges remain such as pass disturbs for a regular Charge Trap NAND string approach. This is the road that Samsung took between 2002 to about 2007 with their horizontal TANOS strings.
    Regards – Andy

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