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Feb 24

ISSCC 2014

Highlights from this year’s ISSCC conference included more details of the Sony/Micron 16Gb ReRAM chip and Samsung’s 3D NAND (V-NAND) chip both of which have featured in recent Forum blogs. The Sony/Micron chip is more accurately described as CBRAM as the cell comprises of a bilayer comprising CuTe on an insulating film which becomes conductive following the migration of Cu ions. The cell has a buried transistor like selector (1T1R) and has a 6F^2 footprint in 27nm technology. The chip is single level and on the face of it would not lend itself to a multi-level configuration. See below for the schematic from the ISSCC presentation. Based on the cell size, I would imagine the reset current be less than 100uA, probably much less. Each cell requires a forming process which itself would add significantly to the cost of the chip if done serially. However, I’m sure the folks behind this technology have some innovative solution(s) in mind.

The Sony/Micron chip was described as an example of a storage class memory (SCM) where performance is better than NAND by slower than DRAM. For example micro second latencies (2uS read, 10uS write) are claimed along with a 1GB/s DDR like interface and a 0.2GB/s write speed. A number of applications were identified such as SCM and a SSD cache. Presumably these first applications would be directed at enterprise systems where the cost premium for the added performance can be absorbed more easily than in consumer products. Sounds encouraging! But of course there is still a long way to go before this technology can prove viable, i.e. profitable.

Samsung presented more detail on their V-NAND chip and plans for development. Their ISSCC presentation described a 128Gb, 2bit per cell, 24 layer architecture fabricated with 40nm half pitch technology. The chip size is a bit smaller than the Micron/Sony ReRAM chip and the Micron 128Gb 16nm planar NAND chip also presented in the same session at ISSCC. (Actually the Micron chip is 16nm half pitch in the word line direction and just over 20nm in the other.) Endurance for the V-NAND chip was quoted 35k cycles which is significantly higher that today’s state of the art planar NAND. Samsung described how the technology would evolve towards a 1Tb chip. Interestingly, they do not envision scaling driven by lithographic shrink. Rather the combination of more layers and possibly more bits/cell are their roadmap towards 1Tb in about 5 years. The back of my envelope suggests this would require 8×24 (192) layers at 2 bits per cell or 128 layers at 3bits/cell. Wow!

Christie Marrian, ReRAM Forum moderator

1 comment

  1. andyjan123

    Regarding Samsung’s V-NAND, I recently did an analysis on their ISSCC presentation and also had an IEEE peer-reviewed cost analysis published – both highly relevant to how ReRAM solutions would compare (in addition to my company’s approach).

    See:

    http://bit.ly/1m6ef0g for ISSCC V-NAND analysis

    http://bit.ly/1imVpBb for IEEE cost paper

    Take-ways: the V-NAND vertical channel “litho-light” approach (applies to p-BiCS too) results in a cell size per layer that is literally huge (30X what 2D NAND can achieve). The only way to increase capacity is to stack and make the NAND strings longer. This kills string current (nA or less).

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