Dec 09

Samsung Analyst Day

Samsung held an Analyst Day at the beginning of November which I missed at the time. In my defence, I don’t normally keep an eye out for such presentations from Samsung as the previous one was 5 years ago! (Other companies such as Micron and SanDisk are much more frequent (and regular)). Mr. Dong-Soo Jun, President of Samsung’s Memory Business had the unenviable task of address the Analysts after lunch and admitted in his preamble that this could be challenging! On the technology side, V-NAND (Samsung’s 3D NAND technology) was confirmed as being manufactured in Korea and being shipped in enterprise SSD products to datacentres where Samsung reported a favourable reception. Manufacturing will expand to Xi’an in China ‘early next year’. V-NAND appears to currently be a single bit per cell technology but Samsung see no technical problems with incorporating multi bit bit per cell in the future.

As in the FMS presentation (see here), Mr. Dong-Soo Jun stressed that performance was at the centre of V-NAND’s value proposition (compared to ‘existing ‘planar NAND, 10x endurance, 2x write speed and 40% less power consumption, although it is not clear from the transcript if the comparison is with the same #bit per cell technology). Mr. Dong-Soo Jun also described V-NAND as being as overcoming the ‘lithography dependent technology paradigm’ which has driven NAND scaling to achieve ‘higher density, lower cost, and better performance’. He further stressed that this has ground to a halt as EUV has been delayed. Another interesting item is that the lithography contribution to CapEx is stated as dropping from 45% for planar to 15% for V-NAND.

ReRAM does not get much of a look-in, not surprisingly in view of the big V-NAND news. However, when it is mentioned in the context of DRAM (rather than NAND). DRAM is facing a limitation at ~20nm and ReRAM is one of the technologies being developed for sub 20nm ‘next generation memory’ products. Samsung also have a 3D DRAM in development but this is based on TSV (Through Si Vias) interconnected stacked chips rather than the V-NAND multi-layer structure.

Christie Marrian, ReRAM-Forum moderator

ps The following is copied from the Q&A session following Mr Jun’s presentation
How should I think about how cost competitive your 3D NAND product is relative to the 1y and 1z products of your competitors?
Currently, V-NAND does not have the scale of planar so it’s tough to directly compare. But if you compare V-NAND and planar over the course of the next few years V-NAND ends up being cheaper. The reason is it keeps scaling where planar is reaching it’s limits.
This continued scaling, without rising costs to do so, combined with future scale of V-NAND is why it is the best choice.
Additionally, it’s endurance and performance gives us entry intro premium segments.
Once the multi-bit technology is ready it will also enlarge the consumer market so we are really excited about V-NAND.

1 comment

  1. admin

    Post updated with a ps on the cost, performance comparison between V-NAND and planar NAND technology…..

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <s> <strike> <strong>