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Sep 17

ReRAM/CBRAM at FMS

David Eggleston, Principal, Intuitive Cognition Consulting*, organized a couple of ‘new technologies’ sessions at last month’s Flash Memory Summit (FMS) in Santa Clara, CA. One of the sessions was devoted to ReRAM and included talks from Chuo University, SK hynix, Crossbar, Sony, Blog sponsors Adesto Technologies and Panasonic. Elsewhere in the FMS program were a couple of ReRAM talks from Stanford University. Most of the talks can be found here.

Several talks highlighted technical/manufacturing issues and so come across as being somewhat negative in tone. However, this should be seen as the next step towards the introduction of a technology which has moved from the domain of the R&D lab (where unbridled optimism tends to reign) to the real world of manufacturing.

An example is the SK hynix talk by SuOck Chung who compares initial expectations for ReRAM vis a vis DRAM and NAND with a current view based on recent array data. First NAND has continued to scale in 2D and now 3D and second, sneak path currents have eroded the initially perceived power advantage of ReRAM. As a result ReRAM is seen as an intermediate between DRAM and NAND rather than a NAND replacement with a focus on performance rather than matching NAND cost per bit. Dr Chung further comments that stacking multiple planes of a crossbar array is tricky and costly so a vertical approach along the lines of Vertical (3D) NAND is needed for cost reduction. Interestingly, the focus of two presentations from Professor Philip Wong’s group at Stanford was exactly this (3D ReRAM). They compared three different architectures and presented some encouraging results from individual cells from a vertical array.

Similar points were made by Dr Amigo Tsutsui from Sony. He reiterated that Sony, through their collaboration with Micron, are still focusing on a 16GBit product in 2015. But it is clear that this will not be a NAND replacement, i.e. primary storage product, simply on the grounds of cost. Dr Tsutsui also points to the need for dedicated controllers to deal with the unique characteristics of ReRAM switching.

Panasonic, on the other hand, were much more upbeat. They have an MCU with ReRAM memory in mass production this year. While this is a low density, the benefits can be seen in terms of system active power and cost. Dr Wei summarized the Panasonic’s extensive work on their TaOx ReRAM cell and switching mechanism and concluded that it is no longer an emerging memory as it has entered mass production!

Hagop Nazarian from Crossbar followed their recent announcements with a comparison of their ReRAM with NAND and NOR Flash and an analysis of an ReRAM based SSD. The superior performance in terms of read/program time and the bit addressability of ReRAM lead to big gains at the system (SSD) level. Further Hagop points out existing memory controllers have to mask NAND’s shortcomings and requires complexity and overhead for tasks such as for L2P mapping, Garbage collection, Wear leveling, Bad block management and ECC. A much simpler controller leads to further benefits for the ReRAM based SSD.

The combination of ReRAM and NAND has been the focus of Professor Takeuchi’s work at Chuo University. His group’s two talks described how using ReRAM to store hot or random data in ReRAM will suppress data fragmentation in the NAND storage and leads to significant gains in system performance. A second example was the use of ReRAM as a parity buffer. The authors reported that if the endurance of ReRAM is 10 million cycles, the required buffer capacity is less than 0.1% of the storage (NAND) capacity. A key point here is that these gains can be realized without ReRAM being cost competitive with NAND. So maybe this is the application that Sony is targeting……

Christie Marrian, ReRAM-Forum moderator with a big thank you to David Eggleston *who can be contacted at [email protected]

9 comments

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  1. Fred Chen

    I am not sure why Hynix included the sneak current afflicted RRAM in a comparison with NAND. Such a system wouldn’t even meet basic error tolerance requirements. It would be more fair to compare a basic 1T1R architecture with NAND. Who needs block erase?

    Obviously fewer layers are processed for the planar 1T1R. That is the cost and complexity advantage.

    1. admin

      Hi Fred
      I cannot speak for Hynix but I suspect they used the crosspoint ReRAM for comparison with NAND because they both have 4F^2 unit cells. A 1T-1R ReRAM will have a larger unit cell and hence not be cost competitive with NAND.
      Best
      Christie

      1. Fred Chen

        I think you’re right, although he also mentions 3D NAND, where I would count layers. But 1T1R is not far off, at least in principle. We’ve seen BJTs used as the transistor, giving 4F^2. Shared MOSFET source gives 6F^2 1T1R, but fewer masks than flash, since array and periphery are very different transistors.

  2. carlos

    Thank you Christie for inviting me to this
    Blog. I would add at this point that I see the there are two types of ReRAMs? One that is a metal/ insulator transition as a bulk phenomena. And others that are localized phenomena, such as filaments and interfacial transitions . The negativity is entering the area of filament more the second type.

    1. Fred Chen

      Hi Carlos,

      Even metal-insulator transition might be localized at defects: http://www.mse.berkeley.edu/~jwu/publications/Fan-PRB-11.pdf

      1. carlos

        Yes Fred, that is my point.Defect driven MIT is what we avoided. For reference see EEtimes “non filamentary ReRAM, a tip from academia” and the May 32st, 2011 issue of Journal of Appl. Phys. By controlling the coordination sphere of TMOs, we show no filaments and a more deterministic switch we also eliminate the Shottky Barriers and have Al and CoSi electrodes. Such technology is truly a correlated electron effect and not a filament switc.

      2. carlos

        Fred,
        I just read your paper. Thank you. You are absolutely right with The Vanadates, as the structural phase transition and the metal Insulator transition from local defects come together. In essence, the the two are inseparable: the lattice distortion and the electronic structure. In the case of NiO and other TMOS , the lattice is not the first order cause o MIT. My work is exploiting disproportionation and not filament growth as the Resistive switch mechanism. We can switch without any Electroforming.

        1. Fred Chen

          Carlos, thanks for your information. Correlated electron effects are interesting, but still not widely understood yet. Has similar MIT been seen in other oxides like PCMO and LCMO?

  3. Chen Yangyin

    I am not sure if the cost of ReRAM will be higher than that of 2D planar NAND at the same technology node.

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