«

»

Sep 11

3D and the Flash Memory Summit

I had an interesting chat with David Eggleston, Principal, Intuitive Cognition Consulting*, about last month’s Flash Memory Summit (FMS) in Santa Clara, CA. Dave organized the couple of ‘new technologies’ sessions (more on this in a subsequent Blog) and participated in a ‘what comes next’ panel (more on that later too). The attendance at FMS was up ~30% from last year which is pretty impressive in these days of more or less continuous conferences. Why? Good question! Dave put this added interest down to the acceptance that Flash is now a fully paid up member of the storage pantheon. While SSDs have been around in laptops and tablets for some time, Flash is now considered an integral part of enterprise performance SSDs.

But it doesn’t end there. One of the FMS highlights was the demonstration of how Flash has been introduced into faster memory channels, i.e. the DIMM sockets you probably have populated with DRAM on the motherboard of your desktop. Servers have many DIMM sockets and apparently only one has to be actually populated with DRAM. Up to now, Flash has been used in DIMM sockets to back up DRAM when a power outage is sensed. The new development is to introduce Flash as an actively used memory with access times far faster than possible with a SSD. The trick is to hide the Flash limitations as working memory behind a controller which interfaces the memory with the rest of the system. Dave refers to this as virtualization in that the actual memory performance characteristics are no longer the concern of the system as they are dealt with by the controller.

Looking further out one can see that it is no longer essential to have a homogeneous memory technology behind the controller and one can mix and match depending on price and performance at any given time. One can do this as logic is so much faster than even the best working memories that there are plenty of clock ticks available for the controller to do its stuff. See above from an IBM presentation by Jung Yoon at FMS. This has an important consequence for ReRAM/CBRAM (and other emerging memories) as it not necessary to be a 1:1 replacement for existing memory and performance enhancements can readily be passed on to the system.

The really big news at FMS was Samsung’s announcement of not just Vertical (3D) NAND manufacturing but also a product (SSD) incorporating 3D NAND chips. A lot of people, not least Samsung’s competitors, were amazed by this development as 3D NAND was believed to be a few years away. 3D is seen as a way to continue NAND scaling, i.e. reduce the cost per bit, by all the big 4 NAND producers. Indeed SanDisk/Toshiba were quite clear about this by pointedly repeating their position from May that 3D NAND is “targeted to provide meaningful cost reduction versus 1Z” (their sub 19nm and possibly last, planar, 2D NAND) and don’t see their 3D NAND appearing until 2016. Samsung have taken an almost opposite tack by pushing 3D NAND as giving a performance enhancement over planar (2x faster and an impressive 10x improvement in endurance) and are pricing their 3D NAND at a higher cost per bit than planar. From Samsung’s presentation!

Christie Marrian, ReRAM-Forum moderator with a big thank you to David Eggleston *who can be contacted at [email protected]

12 comments

Skip to comment form

  1. Fred Chen

    I have always wondered about the relationship between cost and the number of layers in 3D. Obviously you’re depositing layers many more times and etching many more times deeper (more layers as well), compared to 2D planar. Lithography aside, it seems these other costs have been commonly neglected in consideration.

    1. admin

      Hi Fred
      Vertical (3D) NAND has bitlines which are perpendicular to the wafer surface. At present the minimum feature sizes in 3D NAND are relaxed (i.e. cheaper lithography) compared to planar (2D) NAND but the etching (and deposition) challenges are greater. However, due to the costs of tooling and masks, lithography tends to be more expensive than other processes. Double patterning as used in the current state of the art planar NAND is much more expensive than standard lithography as multiple exposures (and masks) are needed along with a number of additional deposition and etch steps.
      Best, Christie

      1. Fred Chen

        Even with relaxed design rules, the lithography is not a straightforward extension from thin films. The thick multilayer would require much thicker photoresist at same design rule to pattern a thicker etch mask. But the main thing, as they say, time is money. Depositing and etching more layers definitely slows things down.

    2. Chen Yangyin

      Hi, Fred:

      You can refer to the following estimation from AMAT, for the process cost shift, from 2D planar NAND to 3D.

      http://www.appliedmaterials.com/sites/default/files/am_2013-03_strategy_profitable_growth.pdf

      Take a look at page.10.

      As you imagine, the deposition and etching cost ramp up for the 3D vertical NAND. The litho is still one of the biggest cost, but its percentage in total process cost decreases.

      When we just look at the economy wise of the 3D NAND, its scaling up in layer numbers is also not sustainable in a long term. Sandisk puts 3 generations of 3D NAND on its roadmap, and I think that’s reasonable. The stacking of CT layers will stop some where, as the deposition / etching become too expensive as well.

      1. Fred Chen

        Hi Yangyin,

        Thanks a lot for the link.

        Here is also a reference on the subject:
        http://in4.iue.tuwien.ac.at/pdfs/sispad2010/pdfs/03-B.1.pdf

        Fred

        1. Fred Chen

          Another link: http://m.semi.org/?url=http%3A%2F%2Fwww.semi.org%2Fen%2Fnode%2F44831#2995

          It’s related to TSV etching but that’s much easier, because of much larger hole, lower aspect ratio, and just etching silicon.

      2. admin

        Hi Yangyin
        Thanks for the link. However, I would urge a note of caution about the interpretation of the chart on page 10. After all, Applied sell etching and deposition equipment, not lithography tooling!
        Thanks again
        Christie

        1. Chen Yangyin

          Hi, Christie:

          You also made the point…

          Page 10 only serves for a reference.

          I got similar comments from some others, as AMAT may be a bit biased in counting the future growth of CVD / etch tool market, according to their current market / technology position.

          1. admin

            Hi Yangyin
            There is no doubt the 3D (Vertical) NAND offers significant etching challenges compared to 2D (planar) NAND. Your original comment is backed up by Micron (who do not sell etching or litho tooling!) on page 30 of http://files.shareholder.com/downloads/ABEA-45YXOQ/2612683327x0x683845/2183f5fc-ced4-439b-8de3-7b251d28f163/Micron%202013%20Fall%20Analyst%20Conference_Handouts.pdf. This is Micron’s Fall Analyst Conference presentation from August 2013.
            Best
            Christie

        2. Chen Yangyin

          Thanks for the sharing, Christie.
          Different memory vendors have their own estimation of total cost of ownership for the 3D NAND.
          Samsung first rolls out the 3D NAND, while others don’t yet. I don’t know exactly what makes Samsung believing that their 3D NAND is financially beneficial, but the first player always has zero opportunity cost. Being a leader, maybe that’s also important.

          1. admin

            Jim Handy (The Memory Guy) has shared ASML’s (litho tooling manufacturer) take on the process steps required for 2D and 3D NAND, thememoryguy.com/3d-nands-impact-on-the-equipment-market/?goback=%2Egde_3434280_member_5836589675581562884
            Not surprisingly its is rather different than AMAT!

  2. Chen Yangyin

    The one from facebook, in proposal of “cold” flash is also very interesting.

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <s> <strike> <strong>