First a caveat: I know something (from a previous life) about neuromorphic computing but what I do know is not much and no doubt outdated at least in part! The concept as I understand it is to mimic in silicon the methods of computation as performed in biological entities. The point being that our brains are significantly better than computers at some tasks (but not all). The other point is that it is now possible to integrate tens of billions of devices (transistors) on a silicon chip i.e. comparable to the number of devices (neurons) in self sufficient organisms. When I last looked, the consensus was that a human brain had the order of a thousand billion devices (neurons). The ReRAM cell (memristor) is seen as a device that has the potential to be one of the unit building blocks of a neuromorphic computer. However, it is not entirely clear to me what precise properties of ReRAM are essential for neuromorphic computing. Maybe someone can help me here.
From time to time reports about progress in the field appear but until now, I’ve always felt reluctant to write about them. (And my attempts to entice others to write had been similarly unsuccessful.) Recently a group at Boise State have received a 3 year NSF grant for the project “CIF: Small: Realizing Chip-scale Bio-inspired Spiking Neural Networks with Monolithically Integrated Nano-scale Memristors.” The same group has recently published a well written paper in the Journal of Low Power Electronics and Applications entitled “Reconfigurable Threshold Logic Gates using Memristive Devices”. The Ag-Chalcogenide devices are used to (re)configure the functionality of threshold logic gates to act as AND, OR, NAND or NOR gates. While not neuromorphic per se, the ability to reconfigure logic functionality on the fly is interesting first step. The paper is based on data from a board level implementation (see image below from the Boise State web site). The Ag-Chalcogenide devices are in the top right part of the board). The authors plan the send out the “first of the new neuron chips out for fabrication within weeks”. I assume this will implement some if not all of the board level functionality in a chip or chips.
However, what really struck me about their paper is that the authors admit their Ag-Chalcogenide devices are not perfect as the threshold voltages for programming shift with device state and time. However the authors describe how this problem can be overcome with an off chip monitoring process (which could presumably be implemented in Si if desired). Describing their devices in more detail, the authors show that erasing (increasing device resistance) is less predictable than writing (decreasing device resistance). The authors discuss how these issues would impact integrated artificial neural networks. They are also planning to extend their approach to neuromorphic computing.
Christie Marrian, ReRAM-Forum moderator