Adesto Technologies held a get acquainted workshop recently in San Jose and David Viera, MarCom Director, was kind enough to forward me the presentation focused on CBRAM. The program started with a company introduction followed by an description of Adesto’s ‘more conventional’ NVM products which they acquired through the deal with Atmel. This puts them in an interesting position of having a full product suite of NVM solutions along with a successor technology. As an (important) aside, Digi-Key have just announced a distribution agreement with Adesto and will feature their serial flash products along Adesto’s CBRAM based products ‘later in 2013’. More on this later in the Blog.
CBRAM is being positioned as more than a pin compatible Flash replacement. Rather it is a NVM solution that has a faster than Flash and lower power than DRAM performance and hence fits into the ‘memory gap’ than has opened up between DRAM and Flash in the memory hierarchy. Given the ability to include the memory behind on chip implementations of existing interface standards (serial, parallel Flash, DDRx, etc.) this is principle will minimize the system level disruption caused by including a new memory tier. The workshop’s presentation by co-founder Shane Hollmer introduced CBRAM as being ‘a disruptive memory technology platform that is highly scalable, low power and high performance’ and can be implemented in a BEOL module in a standard CMOS process. As another (important) aside, their partner Altis Semiconductor has just announced their next generation (130nm) embedded CBRAM technology as part of their 130nm low power platform. Interested parties can participate in multi-product wafer program to mitigate the costs of development.
A couple of charts in Shane’s presentations compared CBRAM to today’s NVM technology. First it is worth emphasizing that low voltages are needed so the space required for a charge pump and the process complexity needed to deal with on-chip high voltages are avoided. Power and speed are the big performance differentiators with improvements of over 4 expected for the CBRAM solutions currently in pre-production yield ramp. There is also a huge improvement in erase speed (which are comparable to write speeds) which will have huge implications when designing cache type applications to fill the memory gap. Further more dramatic improvements such as ~10ns program and erase have been demonstrated in ‘technology demonstrators’.
Finally to Adesto’s roadmap and the sort of products that might soon be available on the (virtual) shelves at Digi-Key. Currently low density (up to 1Mb) EEPROM/NOR Flash products are in pre production ramp and I imagine there are samples out there. These are manufactured with 130nm technology and feature a 20F^2 cell size and are pin compatible with existing solutions. So presumably you can just plug them in and the only difference you would notice is a longer battery life! The next generation of products (up to 128Mb, 65nm technology, 6F^2 cell size) are in development and feature a 150 MHz clock and further power reductions.
Christie Marrian, ReRAM-Forum.com Moderator