At the 2013 ISSCC, Panasonic presented a very detailed paper on improving ReRAM endurance (specifically forming and writing) in the same session as the Toshiba/SanDisk 32Gb chip (paper 12.1). The paper presents an ReRAM analysis based on the oxidation/reduction (redox) mechanism of filament rupture and formation. The authors point to two techniques as critical in improving endurance to the 107 level: 1) Forming and 2) Recovery from intermediate resistance states. Results are presented from a 2x 256kb 1T1R test chip with 180nm CMOS with a 200nm by 200nm Ir/Ta2O5/TaOx/TaN ReRAM cell. The thickness of the layers is not specified.
Forming is a two step process where first a voltage is applied until a resistance drop is observed. This is interpreted as forming an oxygen vacancy channel in the Ta2O5 layer. A second step involves the application of a voltage with the opposite polarity to form the filament within the oxygen channel signaled by a further resistance drop. (See schematic based on their VLSI 2012 presentation) For the first step, the authors see a distribution in the time required for the formation of the oxygen vacancy channel across the array with faster times forming wider channels (I’m not sure how this was measured). For the second step, the pulse current limit (i.e. compliance current) is critical in determining the width of the filament with respect to the channel created in the first step. (Higher compliance currents giving wider filaments). The net result is that the filament can be formed with control sufficient for it to have the potential of being extended to a 16nm process with the algorithms the authors describe.
The recovery from transient resistance states is based on a sequential verify/write algorithm where specific steps are taken if an unexpected resistance state is detected. Two examples are given, both of which appear stable in the sense that they are reproducible under the standard write/erase cycle. The first is an resistance state intermediate between the high and low states. The second is a ‘frozen high resistance state. The intermediate state is interpreted as due to residual oxygen in the filament at the interface between the two Ta Oxide layers (incomplete reduction?). Applying a small opposite polarity (erase) pulse helps dissipate the residual oxygen and recover the low resistance state of the filament. The frozen state is interpreted as residual oxygen at the Ta Oxide interface but with the filament ‘oxidized’ at the interface with the top electrode (as in its high resistance state). This is corrected by applying a larger than normal erase voltage which again dissipates the residual oxygen. In summary, an intermediate state is recovered by a smaller than normal erase pulse and the frozen state by a larger than normal erase pulse.
Results from a 256kb array show 107 endurance with a ~3x ratio between the minimum high resistance and maximum low resistance states. Average ‘on’ cell read current is ~35µA and the current is measured by the discharge time which I interpret as the time to discharge the bit line capacitance (as is often done with NAND Flash) rather than a direct current measurement. The level verify and recovery algorithms appear to be built in on chip.
Very impressive, IMO!
Christie Marrian, ReRAM-Forum-Moderator
Paper 12.6 ISSCC 2013: Filament Scaling Forming Technique and Level-Verify-Write Scheme with Endurance Over 107 Cycles in ReRAM
Akifumi Kawahara, Ken Kawai, Yuuichirou Ikeda, Yoshikazu Katoh, Ryotaro Azuma, Yuhei Yoshimoto, Kouhei Tanabe, Zhiqiang Wei, Takeki Ninomiya, Koji Katayama, Ryutaro Yasuhara, Shunsaku Muraoka, Atsushi Himeno, Naoki Yoshikawa, Hideaki Murase, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono
Panasonic Corporation, Kyoto, Japan