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Mar 05

ISSCC 2013 Revisited

It’s already being referred to as simply “Paper 12.1” from this year’s 60th edition of the ISSCC in San Francisco. Paper 12.1 is of course the Toshiba/SanDisk paper describing a bilayer 32Gbit ReRAM chip. Unfortunately I was not at the conference. A few details of the paper have emerged and some colleagues have been kind enough to pass on a few comments. The chip is a bilayer of two crosspoint arrays fabricated one on top of the other sharing the set of wires (designated as Bit Lines by the authors) fabricated between the arrays. The two sets of perpendicular wires (designated as Word Lines) are situated under and over the bilayer stack. Each cell at the intersection of the Bit and Word Lines comprises of a metal oxide layer and diode access device. Thus the stack of the bilayer (in order of fabrication) is Word Line-Diode/MeOx-Shared Bit Line-Diode/MeOx-Word Line (see schematic from Figure 12.1.1). The composition of the metal oxide (MeOx) was not disclosed. The bilayer is fabricated with a 24nm technology which I assume means that the Word Lines/Bit Lines each have pitch of 2x24nm, i.e. 48nm. This would mean that each ReRAM cell has an area of 4F^2 where F is 24nm. This would give a planar equivalent density of 2F^2 per bit* as there are two layers of cells. At least that is what I would have thought except that one of the figures from the Paper states the cell size is 24nm by 24 nm (F^2)!

The arrays are fabricated in the BEOL over circuitry in the under lying Si. The arrays are organized in ‘Bays’ which each comprise of 32 by 4 (128) mini bilayer cross point arrays which in turn comprise of 2000 Bit Lines and 4000 Word Lines to give 8 million cells per mini array per layer. The chip is currently one bit per cell although the authors believe MLC (and more layers) are possible.

This is an impressive development and shows a huge commitment in terms of design and processing by the two companies involved. The chip looks as if it is a new design with an architecture radically different from that used in today’s flash memory. I’m sure some IP has been reused in the periphery circuitry but the memory core and the connection between core and periphery is radically different. The speaker gave no details of yield and reliability beyond values for the read and write latency. Another indication that this is still really a test chip is that (my back of the envelope estimate of) the array efficiency is low, far lower than a NAND chip for example.

So the bottom line is that this represents a huge advance for ReRAM technology. After all the chip has a 500x greater capacity than the previous ReRAM ‘record’ and incorporates multiple memory layers, another first at this density. Nonetheless, I expect commercialization is a way off with much yield learning and design iterations needed prior to products appearing.

Christie Marrian, www.ReRAM-Forum.com, moderator
*see Comment and the top left part of figure 3 in this link

3 comments

  1. admin

    Vince Khwa got in touch and pointed out that, for a technology node where the minimum feature size is F, the cell size is 4F^2 in a cross point array, i.e. a feature and space in both directions, and multiple layers does not change this. I have made a small edit to the Blog to the point out that the double layer changes the effective size per bit (not cell) to 2F^2.
    Thanks, Vince!

  2. Chen Yangyin

    “The chip looks as if it is a new design with an architecture radically different from that used in today’s flash memory” ?

    You mean the cell structure or the peripherals?

    1. admin

      Just to elaborate on my comment about the architecture. There are enough details in the presentation to indicate that this is a new chip design rather than the re-use of an existing chip design used in NAND or NOR for example. If this is the case it represents a huge amount of work that has gone into the design and debug of the chip layout. The miniarrays and layout of the Bays are described in the presentation and again this is different from any of Toshiba/SanDisk’s existing products (as far as I know). Others have, of course, proposed and implemented such architectures. The periphery circuits (line drivers, sense amps, power supplies, etc, etc) could well be re-used from existing designs with little or no modification. However, compared to a NAND or NOR chips the connection to the core cells is very different as the cells are above the periphery circuits rather than in the same plane.
      Again I should emphasize this is (hopefully) informed speculation on my behalf.

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