There has been lots of talk recently about IBM’s two terminal access device (AD) developed for PCRAM and ReRAM based on MIEC (Mixed Electronic Ionic Conduction). With a highly non-linear IV characteristic (far more non-linear than a pn diode for example), it has been attracting a lot of attention for BEOL memory. It appears to be quite simple in that the material can be sputter deposited and polished (CMP) in a BEOL via with the appropriate top and bottom electrode material(s). While the material is not identified beyond that it contains Copper there is quite a lot of information available on the IBM web site researcher.watson.ibm.com/researcher/….. including the recent IEDM and VLSI Conference papers. The mobility of copper ions is reportedly key to the operation of the device. As opposed to a diode, I like to think of the MIEC device as having a low and high resistance state which can be switched at relatively low voltages, <1V, for example. I was a bit confused by the MIEC name but there is a very detailed review on MIEC material properties available from Elsevier by I. Reiss, Solid State Ionics 157 (2003) p1 – 17. The device can perhaps best be described as MIEC with ion blocking electrodes so that only a small transient component of conductivity is truly ionic (MIEC materials are often used in electro-chemical cells). So while ionic mobility would appear to be important to the operation of the device, conduction is essentially electronic.
The device turns on in either direction once a voltage greater than ~.5V is applied. Below this turn on, the current through the device is essentially zero (<10pA). Above turn-on, the current rises exponentially to give an enormous on/off ratio, 107! Current scales with pore area and the current available is comparable to that identified by the ITRS (International Technology Roadmap for Semiconductors, e.g. Table PIDS8b in www.itrs.net/Links/2012ITRS/2012Tables/PIDS_2012Tables.xlsx) for PCRAM (data plotted above). This is quite significant as there are no other BEOL select devices (that I am aware of) that are capable of switching this level of current density (>10MA/cm2). And of course PCRAM requires a higher current (at the same node) than ReRAM/CBRAM. Endurance at high current densities is sufficient for Storage applications but at lower current densities it has some way to go to meet the requirements for Memory (i.e DRAM like) applications.
IBM has looked at scaling both laterally and in thickness in some detail. Laterally, the devices appear to work as small as they can currently be fabricated (~20nm). In thickness, the leakage current rises as the MIEC material thickness drops below 12nm. Key to achieving this is not just the via formation but also the MIEC material deposition and planarization (CMP) process. At these dimensions sputter deposition is challenging for aspect ratios >1 and CMP can be especially difficult to monitor. Interestingly, the TEM pictures, while impressive, do show some signs of dishing (the material in the via is lower than the surrounding dielectric). Nonetheless I would expect that these MIEC devices should function down to ~12nm in dimension. To be continued…..
Christie Marrian, www.ReRAM-Forum.com Moderator