Unity Semiconductor is a true veteran in the emerging memory/ReRAM field and was recently acquired by Rambus “one of the world’s premier technology licensing companies”. I must admit to being somewhat surprised by this acquisition when I first heard about it. Was this another example of ‘Strange Bedfellows’? Unity is a company with an ambitious product roadmap and always seemed to be a company that aggressively pursued hardware (i.e. chip) development in Fabs around the world. I was fortunate enough to catch up with Dave Eggleston* former CEO of Unity recently and this was the first question I put to him. It turns out my view of both companies was a little off the mark. Unity have been very active in developing an IP portfolio on their CMOx technology and Rambus engage proactively with many customers to tape out and fab their designs in silicon. The match also helped both companies fill needs. In the case of Unity, it gave them stability away from the constant need to raise funding. For Rambus, it gave them an entrée into the non-volatile memory and emerging memory fields along with an existing IP portfolio covering a broad range of technology, design and architecture. It appears that both sides understand the importance and issues associated with technology R&D and building IP portfolios. As a result, the culture mismatch I initially saw between the two companies is not so real.
So what is behind Unity’s success? Dave points to three key Unity innovations:
1) A bi-layer CMOx structure in the ReRAM cell
2) The memory array tile architecture developed around the properties of the cell
3) The compatibility with a vertical ‘crosspoint’ array architecture
The individual cells have a sufficiently non-linear IV characteristic to allow a crosspoint array architecture without an additional select device. There is a caveat that the array must be limited in size (1000’s by 1000’s, for example) but Unity have developed a multi-tile chip architecture that takes further advantage of the tile concept with losing overall array efficiency. Moving to a vertical crosspoint array is vastly simplified by the lack of a need for a select device and eliminates the need for (currently) costly minimum feature lithography. While this replaces the litho challenges with deposition and etching challenges it at least reduces the dependence on ‘waiting for EUV’ (see recent Blogs) or the costly alternatives.
Moving on to PCRAM (phase change), Dave pointed out that this is currently a technology without an apparent home or even niche. As he described in his Flash Memory Summit presentation, PCRAM is not inherently fast enough for main memory (DRAM replacement) and while it is faster than NAND, it cannot combine the density (smallest cell size) and speed of ReRAM for data storage (NAND replacement). PCRAM requires a select device and that and the current levels required, make the translation to a 3D or vertical architecture more challenging.
Looking back, one can often learn! Dave is confident that the system will always adapt to take advantage of new technology. There may be a fair amount of grumbling from the system designers but they know full well that performance gains at the system level are critical. When DRAM was first introduced, many people were horrified by the need for refresh which of course is unnecessary with SRAM. However, the smaller cell size and comparable speed became compelling drivers for improved performance (and lower cost) at the system level. As a result the necessary refresh algorithms and designs were developed and implemented. Another ‘historic’ example of systems changing to adopt smaller memory cell size technology is the transition from NOR flash to NAND flash. This brought about ECC (error correction) and bad block handling techniques which burden the system but allow an imperfect NAND chip (with smaller cell size and cheaper manufacturing) to be used successfully. Dave expects acceleration of the same trend for emerging memories with more complex signal processing algorithms in front of data storage memory (ReRAM). The ability to ship (slightly) imperfect memory is a huge win for the memory makers.
All in all revolution is in the air as system level changes are implemented to eliminate memory bottlenecks and incorporate new memory technologies and hierarchy!
Thanks, Dave, for the de-bemusing.
Christie Marrian, www.ReRAM-Forum.com Moderator