Meeting was last week but presentations may be posted on-line in a couple of weeks. Lots of talk about I/V non-linearity. Happy Thanksgiving and a belated Happy Diwali to Everyone!
Chair: Yi Ma, Adesto Technologies
2:00 – 2:05 Welcome and Introduction
2:05 – 2:35 Memristive Nano-devices: Mechanism, Applications and Challenges, Joshua Yang, HP Labs
2:35 – 3:05 Phase Change Memory: Technology status and direction, Bob Gleixner, Micron Technologies
3:05 – 3:35 On-off Switching Mechanism of Oxide Based ReRAM by First Principle Calculation, Katsumasa Kamiya, University of Tsukuba, Japan
3:35 – 3:55 Break
3:55 – 4:25 Mixed Ionic-Electronic Conduction (MIEC) Selector/Access Devices, Kumar Virwani, IBM
4:25 – 4:55 Tunnel RRAM – Device Features and 1R True Cross-Point Implementation, Rene Meyer, Rambus
ABSTRACTS AND SPEAKERS’ BIOGRAPHIES
Memristive nanodevices: mechanisms, Applications and challenges
Jianhua (Joshua) Yang
Principal Researcher, Hewlett Packard Laboratories, Palo Alto, California, USA
The desire to continually improve computing systems drives both the relentless scaling of existing silicon integrated circuit technology and the search for new technologies. To be relevant, new devices must be both extremely small and capable. Memristive nanodevices (ReRAM if for memory applications) appear to fulfill these requirements and have recently been recommended for additional focus in research and development by the International Technology Roadmap for Semiconductor (ITRS). These devices are two-terminal devices that retain state, which provides many useful properties to complement transistors while enabling increased functionality in integrated circuits. I will first briefly describe the working mechanisms1,2 of metal-oxide switches and a related family of nanodevices,3 along with their potential applications.4,5 Then I will discuss the promises and challenges6 together with some possible solutions to the challenges.7-10
1. J. J. Yang et al., “Memristive switching mechanism for metal/oxide/metal nanodevices” Nature Nanotechnol. 3, 429 (2008).
2. F. Miao et al., “Anatomy of a Nanoscale Conduction Channel Reveals the Mechanism of a High-Performance Memristor” Adv. Mater. 23, 5633 (2011).
3. J. J. Yang et al., “A Family of Electronically Reconfigurable Nanodevices” Adv. Mater. 21, 3754 (2009).
4. J. Borghetti, et al., “‘Memristive’ switches enable ‘stateful’ logic operations via material implication” Nature 464, 873 (2010).
5. Q. F. Xia et al., “Memristor-CMOS Hybrid Integrated Circuits for Reconfigurable Logic” Nano Lett. 9, 3640 (2009).
6. J. J. Yang et al., “Metal oxide memories based on thermochemical and valence change mechanisms” MRS Bull. 37, 131 (2012).
7. J. J. Yang et al., “The mechanism of electroforming of metal oxide memristive switches” Nanotechnology 20, 215201 (2009).
8. J. J. Yang et al., “High switching endurance in TaOx memristive devices” Appl. Phys. Lett. 97, 232102 (2010).
9. J. J. Yang et al., “Engineering nonlinearity into memristors for passive crossbar applications” Appl. Phys. Lett. 100, 113501 (2012).
10. J. J. Yang et al., “Diffusion of adhesion layer metals controls nanoscale memristive switching” Adv. Mater. 22, 4034 (2010).
Jianhua (Joshua) Yang Biographical Sketch
Jianhua (Joshua) Yang is a principal researcher at Hewlett-Packard Labs, leading the ReRAM (Memristor) device study effort. His current research interest is Nanoelectronics and Nanoionics, especially for memory and computing applications, where he authored and co-authored over 100 papers in academic journals and international conferences, and holds 15 granted and over 60 pending US Patents. In the last 3 years, he has been invited to international conferences or universities to give over 20 invited talks, keynote speeches or seminars. He recently guest-edited two journal special issues on Non-volatile Memory technologies for Nanotechnology and Applied Physics A, respectively. He was the chair of the 8th IEEE nanotechnology Annual Symposium (SFBA) on ‘Emerging Non-Volatile Memory Technologies’. He also serves as a co-editor of Applied Physics A. He obtained his PhD from the University of Wisconsin – Madison in Material Science Program.
PHASE CHANGE MEMORY: TECHNOLOGY STATUS AND DIRECTION
Bob Gleixner, Micron Technologies
Over the past decade, significant progress has been made in taking phase change non-volatile memory from the research stage to production devices. The underlying technology for these devices is based on chalcogenide materials that can be reversibly converted from a high conductivity crystalline phase to a low conductivity amorphous phase. When integrated into a memory cell, this material enables non-volatile memory devices that provide a combination of performance and cost not achievable with conventional floating-gate technologies. This presentation will first review the basic operation of a phase change memory cell. It will then discuss various schemes for integration into a memory array. Finally, it will consider scaling challenges for phase change memory and directions for future development.
Bob Gleixner’s short biography
Bob Gleixner is a Senior Member of Technical Staff with Micron’s Process Research and Development team in San Jose, CA. He received his B.S. degree from Cornell University and his M.S and Ph.D. degrees from Stanford University, all in Materials Science and Engineering. He joined Intel’s logic technology group in 1998 and for the next 10 years focused on reliability in semiconductor logic, memory, and microdisplay devices. In 2005 he started working on phase change memory, leading the reliability team that released the first high-density production product in 2010. In 2008 he joined Numonyx (a spin-off from Intel and ST Micro) and in 2010 joined Micron Technologies as part of the Numonyx acquisition. Bob continues to work on developing emerging non-volatile memory technologies, with a focus on understanding, modeling, and improving reliability to achieve production-capable devices.
ON-OFF SWITCHING MECHANISM OF OXIDE BASED RERAM BY FIRST-PRINCIPLE CALCULATION
Katsumasa Kamiya, University of Tsukuba, Japan
We study the ON-OFF switching mechanism of oxide-based resistive-random-access-memories (ReRAMs) using first-principles calculations. Electron deficient vacancies (Vo) up to 1+ charge states would stabilize a cohesive filament, while further electron removal will stabilize the disrupted Vo configurations with 2+ charges. The Vo cohesion-isolation phase transition upon carrier injection and removal is shown to be a strong driving force in the ON-OFF switching process. We also propose that bipolar or unipolar behavior is determined by how the carriers are injected into Vo. The control of the carrier injection by the electrode material selection is essential for desired bipolar switching. On the basis of our calculations, we also discuss the effects of the insertion of Al2O3 thin layer into ReRAMs, which has shown to improve drastically the ReRAM properties.
Katsumasa Kamiya’s short biography
Katsumasa Kamiya was born in 1978 in Tokyo, Japan. He earned his doctorate at University of Tsukuba in 2006. Currently he is an assistant professor at graduate school of pure and applied sciences of University of Tsukuba. He specializes in computational nano-science, particularly density functional calculations for nano-materials ranging from hard to soft materials.
MIXED IONIC ELECTRONIC CONDUCTION (MIEC) SELECTOR/ACCESS DEVICES FOR NOB-VOLATILE MEMORY
650 Harry Road, San Jose CA 95120
The talk traces the development of Cu-based mixed ionic electronic conduction (MIEC) bi-directional, diode-like selector devices for non-volatile memory (NVM). Such selector devices are highly suitable for NVM candidates such as resistive random access memory (RRAM), magnetic RAM (MRAM), conductive bridge RAM (CBRAM) and phase change memory (PCM) that are under active R&D. An approach for these emerging NVM technologies to be cost competitive with flash memory is high density stacked NVM + selector devices in 3-D cross-point architecture. Such architecture requires a selector device to deliver high-current density (>15MA/cm2) with low off state leakage (~10pA), so that the high ON/OFF ratio (>107) enables large arrays. In addition, for stacking the selector device needs to be back-end-of-line compatible and for certain RRAM candidates the selector device needs to operate in both voltage polarities. We present pulse & DC I-V characteristics, endurance and scaling results on various configurations of small (tens to hundred devices) and large (512 k-bit) arrays of MIEC selectors. MIEC selectors have also been used in 5×10 arrays to drive PCM elements to demonstrate stacked selector memory cells. As a future outlook, we discuss approaches to further improve MIEC selector / access devices.
Kumar Virwani’s Biography
Dr. Kumar Virwani is a Research Staff Member at the IBM Almaden Research Center in San Jose, California. He obtained Bachelor of Engineering (BE) degree from the University of Mumbai, India and MS and PhD degrees from the University of Arkansas at Fayetteville, USA. He worked at Burker Nano from Oct 2006 to Sep 2008 on various aspects of scanning probe microscopy. Since 2008, his research activities at IBM include application of electrical SPM techniques to analyze mixed ionic electronic conduction materials and devices, non-volatile memory materials, nano-indentation of low-k dielectrics and Auger.
TUNNEL RRAM – DEVICE FEATURES AND 1R TRUE CROSS-POINT IMPLEMENTATION
Rene Meyer, Bruce Bateman, Jian Wu, and Christopher Chevallier,
Emerging non-volatile memory technologies based on metal oxides are considered viable candidates to replace NAND Flash in the ultra-high density memory segment. Device attributes of the memory technology have to enable a cost and area efficient implementation to find acceptance in the market.
The most area efficient architecture is a transistor-less cross-point array that features the memory element in series with a select device that reduces sneak currents in the unselected bits. Such sneak currents limit the array size, dramatically increase power consumption in the array and increase voltage drops along the wires. Voltage drops along the wires force the beginning of the wire to be over-driven in order to apply the correct voltage to cells at the end of the wire. This overdrive increases read and write disturb of cells at the beginning of the wire.
Substantial efforts are being made by industry and academia to develop such select devices. Key attributes of the select device are the ability to conduct high currents, a steep and highly non-linear IV curve, and tight control of the threshold voltage.
An alternative approach to a selector device is to design the select property into the memory cell itself. Benefits are a reduction of the operation voltage, simpler processing, and less cell-to-cell variations. In this presentation we will discuss the device features of the tunnel RRAM cell. The tunnel
RRAM combines the functions of a memory device and a selector device and exhibits a desirable highly nonlinear IV characteristic. Key parameters of the non-linear IV characteristic are the ratio of program/ erase currents between a selected device and a half-selected device of >20. In combination with a read scheme using floating partially selected cells, the ratio of read currents between a selected and unselected device is >500. Such characteristics enable cross-point arrays of 8Kbits by 256 bits. The circuit implementation scheme for such arrays results in highly dense, true cross-point memory layouts. The characteristics and model for the tunnel RRAM devices will be described as well as array simulations and electrical data of passive cross-point arrays built to validate the approach.
Rene Meyer’s short biography
Dr. Rene Meyer leads the non-volatile memory device development in the NVM group of Rambus. Rene received a PhD degree and a Diploma degree in Electrical Engineering from the RWTH Aachen University of Technology, Germany. He worked as a post doc at the Research Center Juelich, Germany, and in the Materials Science and Engineering department at Stanford.
In 2006, Rene joined Unity Semiconductor, recently acquired by Rambus, to develop a novel oxide based non-volatile memory. At Stanford he continued his research on fundamental properties of ultrathin oxide films as a consultant assistant professor. Rene has given more than 25 invited presentations in the fields of ionic electronic transport phenomena in oxides and oxide thin film devices. His work includes dielectrics, ferroelectrics, ionic conductors, and oxide based resistance change memories. Rene has published more than 20 papers and holds several patents.
All presentations will be requested to be posted on the CMPUG, PAG and TFUG Proceedings webpages within 1-2 weeks following the meeting date.
If you would like to sponsor this meeting or list a banner ad on the User Group website, please check out our “NCCAVS Marketing/Sponsorship” opportunities at: http://www.avsusergroups.org/misc_pdfs/form_ug_sponsor.pdf