Digging a little deeper into Yan Borodovsky’s (Intel) presentation at the EUV Workshop in June, he states that it should be possible to meet the requirements of Intel’s 10nm (~20nm half pitch) node with 193nm immersion (193i). (Fred Chen pointed me to another Intel reference to this effect, see last EUV post). However he points out that this will require multiple mask exposures (i.e. expensive) and the resulting edge placement errors could cause issues (i.e. yield loss, i.e. expensive) for the cut steps necessary to define features in the 40nm pitch dense array formed (presumably) by double patterning and 193i. He points out that these cut steps will benefit from EUV lithography as edge placement errors can be reduced and the number of exposures reduced (i.e. net cost saving even if EUVL is more expensive than 193i). So it looks as if Intel do have a backup (non-EUVL) strategy for the 10nm node but it would be less cost effective.

Going back to the EUV source issue (schematic of one variant in photo above), Intel makes a compelling argument that the requirement for 250W is actually too low to meet the requirements of high volume manufacturing (HVM). This argument is based on photon statistics (shot noise). Basically, one needs so few EUV photons to expose a contact via that the random arrival rate of the photons from the source alone will result in an unacceptable manufacturing yield. For NAND, there are a couple of key differences in architecture but the back of my envelope suggests the situation will be comparable to that described by Intel. A crosspoint array with vias at the crosspoints, however, could also be challenging (although the contacts will be more regular than on a CPU). While I am not familiar with the ReRAM architecture being developed by SanDisk, I can understand why EUV is needed for a planar architecture. A summary of Intel’s argument follows.

Let’s say we need N photons to expose a contact hole. Further let’s say that we will get an acceptable (yielding) result if we have between N-x and N+x photons to expose the contact hole. This means that we have an exposure latitude (EL) of 2x/N. A good working value of EL is 10%, i.e. we would like variations in our exposure to be less than +- 5%. Let’s ignore all variations from the source except that due to the random nature of the emission of the photons from the source. This is governed by Poisson statistics which can be like all statistical distributions can characterized by a standard deviation. For Poisson statistics, the standard deviation (sigma) is simply the square root of the mean (N in our case). So let’s redefine x as a number of standard deviations, n, i.e. x = n times the square root of N. This allows us to come up with an expression relating N to n and EL.

N≈(2n/EL)^2

Picture a Bell curve with mean N and wings out beyond N+n*sigma and N-n*sigma. The area in the wings will correspond to contacts where the exposure is too high or too low and thus be non-yielding. To work out an acceptable value for the wings, we have to know the number of contacts we want to print and what level of non-yielding contacts we can tolerate. On today’s chips the number of contacts is enormous (>10^9 on Intel’s 22nm node CPU) and we can only tolerate a small yield loss due to contacts (~1%). We can then approximate the required yield per contact and get a value of n which turns out to be around 7. Thus given our required exposure latitude (EL) we can calculate a value for N, the average number of photons required to expose the contact hole. For n=7 and EL of 10%, this corresponds to N of ~20000, i.e. we need an average number of photons per contact hole exposure to be about 20 thousand. This turns out to require a ~4x higher power EUV source than that quoted above.

Christie Marrian, www.ReRAM-Forum.com Moderator

ps I tracked down a poster by Lee et al similar to the paper that is referenced in the Intel EUV presentation. It dates from 2002 and basically says that shot-noise would not be a problem for EUV (because at that time they were talking about 50nm contacts for a sub 100nm node)!

www.sematech.org/meetings/archives/litho/euvl/20021015/Poster%20presentations/Poster%2029-Intel-Lee.pdf