Nov 05

Waiting for EUV (another view of the ReRAM roadmap)

It is ‘Quarterly’ financial report time for many companies and one can occasionally find some interesting snippets in the transcripts of the calls which normally accompany these announcements. For example, SanDisk appear to have an encouraging quarter, reversing sales declines seen through Q1 and Q2. However, what caught my eye was this quote attributed to SanDisk’s CEO Sanjay Mehrotra “We also believe that 3D ReRAM will not start production until sometime beyond 2015 given its need for EUV lithography, which is still in development phase.” (A similar comment is buried in the presentation made by SanDisk at their Analyst’s day in February this year.) This is somewhat more conservative than other company’s roadmaps as we have discussed here. Coincidentally the annual EUV Lithography Workshop has just been held in Hawaii in June and the more recently, the EUV Source Workshop held in Dublin in October. Both the EUV Workshops have full proceedings on-line at www.euvlitho.com. I’m speculating that SanDisk see the need for EUV for contact vias in their ReRAM cell so in a bit of a departure from our regular Blog focus, I thought I would take a look at EUV as it appears to be a key factor in the ReRAM roadmap of at least one major memory company.

It is only too easy to be pessimistic about EUV lithography ever being ready for high volume manufacturing (HVM). The challenges are immense and it is easy to forget what a radical departure EUV is from existing critical layer high volume lithography which is based on 193nm radiation exposing wafers immersed in water. EUV (13.5nm) requires vacuum and the only optics available are mirrors (with a complex multilayer coating and a theoretical reflection coefficient of around 70%, i.e. well less than unity). The mask is also reflective unlike the transmission masks used at 193nm. Nonetheless you can now purchase a tool that will expose 300mm wafers at EUV such as ASML’s NXE:3100. However, no one, least of all ASML pretends that the tool is useful for HVM.

Why? The bottom line is that existing EUV sources do not produce sufficient usable power at 13.5nm. The requirement for HVM is ~250W and current tooling is ~10W (See slide 36 of an excellent overview by Soichi Inoue of the EUVL Infrastructure Development Center www.euvlitho.com/2012/P3.pdf.) The EUV Source Workshop shows some encouraging developments but no one is yet claiming they have a suitable 250W EUV source (I’ll return to this issue in a subsequent Blog).

The general view from the logic (CPU) community is that EUV will be needed for HVM in the 2015/2016 timeframe with Intel stating a clear need for EUV in 2015 to maintain their technology roadmap. However, I suspect that the memory folks would like it a lot sooner. This is because memory, especially NAND is currently being manufactured (at the bleeding edge) at a half pitch* of ~20nm. The logic/CPU folks have different issues and their current leading edge manufacturing (Intel) corresponds to a half pitch of ~40nm (which somewhat confusingly is referred by everyone, not just Intel, as the 22nm node). Broadly speaking ~40nm half pitch is the accepted limit for 193nm immersion. Going smaller requires double patterning which is already used by the memory folks to double the spatial frequency of lithographically defined features to achieve ~20nm half pitch. Going below ~20nm will require even more complex (i.e. expensive) processing of features defined with immersion 193nm lithography. The following from SanDisk’s Analyst presentation describes the situation rather more graphically!

So I suspect that the leading memory manufacturing companies would definitely want to use EUV as soon as it is available.

So when will EUV be available for HVM? My crystal ball is very cloudy (as I suspect are many others) on this question as it would be foolish to underestimate the technical challenges that remain. EUV source development is clearly critical. In addition there are the issues of system integration and infrastructure which present radically different challenges compared to 193nm immersion lithography. However, Intel presents a convincing argument as to why it will be needed and for them it is needed for HVM in the 2015 time frame. So maybe that is why SanDisk are being a little more cautious than other companies with their roadmap for ReRAM.

Christie Marrian, www.ReRAM-Forum.com Moderator

*half pitch is used by NAND folks to describe their technology nodes. This means that the densest features on a chip have a dimension of the ‘half pitch’ and are separated by a ‘half pitch’ sized space.


  1. Fred Chen

    I am a bit surprised why Sandisk would insist to have their ReRAM depend on EUV. Given that 3D NAND development is already proceeding without EUV, 3D ReRAM would follow along the same development lines. It doesn’t make sense to have a promising technology’s development hinge on another technology which only adds risk. EUV has power consumption and resist pattern definition and also mask blank defect issues which are too difficult to resolve by 10 nm at 2015/2016.

      1. admin

        Thanks, Fred, for pointing this out. I’m sure Intel must have a back-up strategy. See the Nov 9th Blog.

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