The recent (August) flash memory summit in Santa Clara had a session devoted to ReRAM as well as featuring prominently in the keynote address by Sung Wook Park of SK Hynix. His excellent presentation is available here and it has some wonderful slides including #3 which compares the best aspect ratios achieved by semiconductor manufacturing engineers and civil engineers. (The semiconductor folks currently lead by over 4x!). The talk includes a summary of NAND’s well known scaling issues along with approaches to 3D NAND. The most interesting part (to me at least) is and a review of SK Hynix next generation memory development. It turns out that they are working on three different technologies: PCRAM (phase change RAM) with IBM, STT-RAM (next gen MRAM) with Toshiba and the better known ReRAM program with HP. The HP collaboration has been ongoing since 2010, the other two collaborations date publicly at least from earlier this year. SK Hynix have a vision for the three apparently competing new technologies which I’ll go into more below. Nonetheless I wondered if the additional collaborations were a reaction to internal concerns about the progress of their longer standing collaboration with HP.
STT-RAM is seen as the ‘replacement’ (successor would be a better word, IMO) to DRAM based on scalability (i.e. more civil engineering like aspect ratios) and, more importantly, essentially infinite endurance. Presumably, SK Hynix do not see this level of endurance being possible in technologies where one is moving atoms around (PCRAM and ReRAM). However, the case for distinguishing PCRAM and ReRAM seems less clear. ReRAM is shown as being closer to the hard drive in terms of cost effectiveness and retention but with higher density and lower performance as compared to PCRAM (see figure above). However, I would argue this is a function more of the chip architecture as shown in the presentation. (PCRAM is shown with a selector/cell with ReRAM in stacked multi cross bar array with no selector device relying on the non-linear I-V characteristic to ameliorate the sneak current issue.) Judging by the size of the test chips shown (1GBit vs 8MBit, quite a contrast to Toshiba’s recent numbers, see Blog dated Sept 28), PCRAM seems to be somewhat further along the development process. However, surely one could build the ReRAM in the same architectures as the PCRAM and/or stack multiple layers of the PCRAM (as indeed is suggested on one of the slides).
All in all, the SK Hynix presentation seems somewhat down on their ReRAM program/collaboration. Endurance of >10^4 cycles is quoted (compared to ~ 10^15 for STT-RAM) although I couldn’t see a figure for PCRAM. But perhaps most telling was the quote attributed to the presenter that: (ReRAM is) “still a ways away. We need a better understanding of the underlying mechanism and its reliability”. This does seem difficult to reconcile with HP’s recent view that “If you know what you’re doing – and there’s a lot of intellectual property involved – literally any foundry could make memristors (ReRAM, my addition) tomorrow.”. I should add that I was not present at either meeting so I am relying on 3rd party reports of the quotes.
Whatever the actual situation is, another excellent point is made by Dr Park that any new memory technology will have to either a drop in replacement for existing DRAM or NAND products or have such a compelling performance advantage that a ‘system’ will be built around it to take advantage of that capability.
Christie Marrian, www.ReRAM-Forum.com Moderator