Most companies in the memory business have ReRAM on their radar if not their roadmaps (See News posts from May). However, I was quite surprised when I came across a story from July describing Toshiba’s R&D in this area. The story http://techon.nikkeibp.co.jp/english/NEWS_EN/20120713/228338/ reported a briefing given by the Toshiba on its Research and Development strategies a few days earlier. What struck me in the report was the statement that Toshiba planned to ship samples of its three dimensional NAND flash (BiCS) at the same time as samples of ReRAM (prototype samples 2013, engineering samples, 2014). So much for the comment that I have repeatedly made here at www.ReRAM-Forum.com that no large company is going to release a new technology (let alone two) on a roadmap that potentially competes with its own product! Furthermore, Toshiba reportedly showed an image of a 64 GBit test chip at the presentation. Wow! That is far larger capacity than any other ReRAM chip that I am aware of and corresponds to approximately 20nm minimum feature sizes if it is a single layer, 1bit/cell, chip (~40nm features for two layers etc.). This represents a massive investment in terms of design and process innovation even for a large company such as Toshiba. By contrast Hynix reported in August at the Flash Memory Summit a ReRAM technology update showing a ‘schematic of a 4-plane 8 Mbit ReRAM chip’ and a related image. (Hynix have been working with HP on this project for some time. More of this in a subsequent Blog.)
Back to Toshiba and the 64 GBit ReRAM chip. Could they really be that far ahead of one of the other leading ReRAM developers and are prepared to risk competing with their own products? Toshiba’s website does have a presentation from the July 10th R&D briefing http://www.toshiba.co.jp/about/ir/en/pr/pdf/tpr20120710e.pdf and the date matches the news story mentioned above. So I eagerly looked for the image of the 64 Gbit chip. Well, there is an image labelled ReRAM and I sorted of persuaded myself that it could be a high density cross bar structure over some much larger wiring. Impressive, but is it from a 64 Gbit chip? Of course I have no way of telling if the feature sizes are compatible, let alone if the structure shown is part of a multi Gbit test chip. And I was not at the briefing although I have seen the same story (with the same quotes) in various places. But I couldn’t help thinking that if I had a 64 GBit test chip in a technology that many of my competitors were striving for, I would certainly put a nice image in my presentation.
So what is going on? I should point out that from this point on I am speculating, pure and simple. Maybe there was an unintended miscommunication about the goals of Toshiba’s two development programs? Possibly the ReRAM test cell is at the equivalent density of 64 GBit full chip? But just after the R&D briefing, Toshiba announced that Toshiba are cutting back on their NAND production (by ~30%). So if nothing else the timing is unfortunate. However, one should perhaps bear in mind that announcements of successor technology(ies) are often aimed at reassuring investors rather than impressing technologists.
Christie Marrian, www.ReRAM-Forum.com Moderator