The 2nd International Workshop on Resistive RAM takes place October 8 to 9, 2012 at Stanford University, CA. The workshop is jointly organized by IMEC (details of IMEC’s ReRAM program ) and Stanford’s NMTRI (Nonvolatile Memory Technology Research Initiative), an industrial affiliate program at Stanford http://nmtri.stanford.edu/. The workshop follows on from the highly successful 1st workshop held at IMEC a year ago.
The workshop program has just been updated and represents an excellent cross section of papers on RRAM and CBRAM not just from the two organizing groups but from across the Globe. The conference kicks off with a couple of keynote talks, the first from Dirk Wouters from IMEC discussing HfO2 based ReRAM. The second is from ARM Fellow Rob Atkin talking about ‘Design Requirements for embedded RRAM’. I would suspect that these are low power, low power, and low power (to paraphrase the old realtor joke about the three most important things to consider when buying a house*). Nonetheless I expect a lively and well illustrated talk. The remainder of the program features seven sessions on ReRAM/CBRAM materials, applications, mechanisms selectors and modeling along with two panel sessions. The first panel session asks whether RRAM or STTRAM will be the ‘winner’ with an international panel from industry and academia. The panel make-up (on which the organizers are to be congratulated) suggests it will be a lively discussion but I doubt if the representatives from Qualcomm, Micron and Hynix will admit that they have already written off one of these two emerging memory technologies. Having said that, I know which one I would be emphasizing if I were in a position to do so. (Hint cell size, power dissipation and the web address of this Blog!). The second panel session is on selectors for resistive memories. This is topic is not often given the level of prominence that it requires. It goes without saying that no ReRAM/CBRAM cell is going to make it any form of volume production unless it is paired with a selector which is compatible in terms of size and performance. Again my hat is off to the organizers for featuring this topic in the panel discussion and preceding sessions.
It is always interesting to see who is going to be speaking at this type of meeting along with the subject matter. In addition to the international representation, I was struck by representations from three local (local to Stanford that is) companies. First is Blog sponsor Adesto who will no doubt be discussing the latest in CBRAM. The second is Intermolecular whose technology is based on combinatorial material processing for the semiconductor and clean tech industries. Looking through their website, there is a strong implication that Intermolecular have been working with Toshiba who are slating ReRAM for engineering sampling in 2014. It will be interesting to see what they disclose. The third company is Rambus or more particularly the former Unity Semiconductor purchased by Rambus in February this year. What intrigued me about their presentation is the title ‘Tunnel RRAM-…’ Should be interesting!
Unfortunately I have to be somewhere else during this week in October. Please let me know if you are attending would be interested in writing something on the sessions or panel discussions.
Christie Marrian, www.ReRAM-Forum.com Moderator
*location, location, and location