Sep 14

SSD Buffer

Back in June at the VLSI meeting in Hawaii, Professor Ken Takeuchi’s group (Chuo University, Japan) presented a paper describing an NAND Flash 256GB SSD (solid state hard drive) with an 8GB ReRAM buffer (I expect CBRAM technology could also be used). A colleague pointed me to a couple of reviews, links below. Professor Takeuchi has long been interested in the utilizing new technology to improve performance and, especially, reduce power consumption, of current technology. Hence the investigation of how to reduce the cost of ownership of an SSD. The paper describes results from emulations of various configurations of the ReRAM buffer and SSD. The main source of performance gains relies on the ability to do frequent random access writes to the buffer which allows the way the NAND Flash of the SSD is accessed to be reduced and optimized. As these SSD writes are of larger size, fragmentation and energy consumption are reduced. Further, the lifetime of the SSD would be increased as there is a correspondingly lower requirement in terms of endurance (as the buffer takes the bulk of the writing of small amounts of data). All this adds up to improved cost of ownership even allowing for extra cost of the complete system.

The gains quoted are impressive, even more so when a system of stacked chips connected by TSV’s (through silicon vias) is analyzed. At the heart of the system is a controller incorporating algorithms controlling the way the data is stored in the various levels of the stack. The emulation was performed using data from a financial application (which apparently is very random access intensive and hence benefits from the ability to make random access writes to the buffer). Of course a suitable ReRAM chip currently does not exist and TSV technology, although rapidly evolving, is currently not sufficiently mature. So is this a compelling ReRAM application to justify and drive the further development of standalone ReRAM? My initial thoughts were positive but then a couple of concerns crept in. First let me be clear that if an ReRAM/CBRAM chip existed, even if it were significantly more expensive than NAND, this would be a compelling application for the reasons the authors point out. However, ReRAM is not sufficiently mature but other forms of higher performance non-volatile memory do exist. For example, obvious choice would be NOR Flash (NOR has a random access type architecture). It would be interesting to see results from the authors based on this idea. I suspect the results would be less than compelling if only for the reason that if they were compelling, somebody would have already incorporated a NOR flash buffer in an SSD!

To develop a multi-GB standalone ReRAM/CBRAM chip will be a massive undertaking and I suspect the application we are discussing here will not sustain the cost both in terms of expenditure and resource allocation. And if the development were to be successful, a company runs the risk of competing with its existing products unless a sufficient number of similar niche applications emerge rapidly. The bottom line is that SSD buffer chip would require a similar level of development as that of a pin compatible Flash replacement. This will happen but not for several years. Instead, the way forward lies in developing ReRAM/CBRAM for embedded applications such as SoC (system on a chip).

But then, I almost hope I am wrong!
Christie Marrian, www.ReRAM-Forum.com Moderator

http://techon.nikkeibp.co.jp/english/NEWS_EN/20120614/223032/?P=1 http://www.extremetech.com/computing/131202-japanese-team-boosts-nand-flash-durability-and-performance-with-reram-buffer

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