Monthly Archive: September 2012

Sep 30

IEDM 2012


Updated October 2nd. The technical program for IEDM 2012 in San Francisco has recently been published. By my count there are 18 papers on various aspects of ReRAM/CBRAM technology. Further, these papers are not just in sessions devoted to ReRAM or Memory Technology sessions but also sessions devoted to Modeling, Reliability, and Design. …

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Sep 28

ReRAM Roadmap


Most companies in the memory business have ReRAM on their radar if not their roadmaps (See News posts from May). However, I was quite surprised when I came across a story from July describing Toshiba’s R&D in this area. The story reported a briefing given by the Toshiba on its Research and Development …

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Sep 19

2nd International Workshop on Resistive RAM


The 2nd International Workshop on Resistive RAM takes place October 8 to 9, 2012 at Stanford University, CA. The workshop is jointly organized by IMEC (details of IMEC’s ReRAM program ) and Stanford’s NMTRI (Nonvolatile Memory Technology Research Initiative), an industrial affiliate program at Stanford The workshop follows on from the highly …

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Sep 14

SSD Buffer

Back in June at the VLSI meeting in Hawaii, Professor Ken Takeuchi’s group (Chuo University, Japan) presented a paper describing an NAND Flash 256GB SSD (solid state hard drive) with an 8GB ReRAM buffer (I expect CBRAM technology could also be used). A colleague pointed me to a couple of reviews, links below. Professor Takeuchi …

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Sep 11

Patent Alert: Part 2

In following up on the last Blog describing the patent issued to inventors at Micron in August, I came across two other patents issued to Micron in July related to ReRAM devices and fabrication. They are very different (no surprise there) but not just in content! The more recent (US patent 8,223,539: GCIB-treated resistive device, …

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