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Aug 24

Patent Alert


“Resistive RAM Devices and Methods” is the title of a patent that has just (August 14th) been issued to Micron in Boise, Idaho. Keeping track of patents can be (for me at least) a very time consuming activity due largely to the rather convoluted language that patent attorneys tend to use. In this case, the language is not as difficult to follow as in some cases and the patent has the good sense to include a reference on which I am an author! The patent describes methods of fabrication of crosspoint array type RRAM devices using processes that, as you would expect, are commonly found in today’s semiconductor Fabs. The basic architecture described is that of perpendicular word and bit lines with vias at the intersections. There is a fair amount of description of how the vias can be filled and the resistive material formed, including the method of filling the via with a metallic material and then partially oxidizing the metal in the via. While I can see problems in maintaining the uniformity of this process over a 300 (or even 450) mm wafer, this method has the great advantage of burying the oxide/conductor interface during its formation. Various materials are mentioned, but only two are specifically mentioned for this oxidation in situ process (which surprised me somewhat). The claims go on to describe single and dual (where a single metal deposition step is used for the wiring and via fill) damascene processes for forming the upper electrodes but in this case the RRAM material is deposited as a blanket film over pre-patterned trenches and vias. The top electrode material is then deposited and polished back in a damascene process to form the top electrodes and top level of wiring for the cross point array type architecture.

Also of interest in the patent is a short paragraph that appears to describe a viable alternative to the damascene process, namely patterned etching of metal material. The paragraph then goes on with a sentence that starts “However, there are several drawbacks…” which even in patent language suggests to me that this process is liable to be exceedingly difficult to control!

This is the first of an occasional series discussing recently issued patents. Often there is more to a patent than meets the eye but in this case it seems clear that the inventors would wish to protect the potential value of their invention(s) in terms of manufacturing high density RRAM devices.

If you have just had a patent issued or know of a recent issue of a patent of interest, please let me know.

United States Patent 8,241,944, Inventors: Joseph N. Greeley (Boise, ID), John A Smythe. (Boise, ID). US Patent Office reference: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,241,944&OS=8,241,944&RS=8,241,944

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